The wavelet- or wavelet packet-based power quality disturbance (PQD) signal detection is highly sensitive to random phase offset owing to their shift-variant characteristics, which has not yet been well discussed in the literature. In this letter, we newly define the wavelet packet transform modulus (WPTM), introduce the two WPTM metrics (MV and RMS) with an optimum factor k modifying conventionally defined universal threshold, and present a WPTM-based PQD detector using those metrics that is robust against severe channel conditions with random phase offset. Simulation results verify that the presented method greatly reduces false edge detection rate (FER) (<10%), while maintaining a high detection rate (DR), when compared to existing wavelet- or wavelet packet-based methods.

High-Efficiency Video Coding (HEVC/H.265) is the latest video coding standard used in various applications. In HEVC, the quality of the reconstructed video is enhanced by two in-loop filters (Deblocking filter and Sample Adaptive Offset filter). In this paper, we propose an efficient resource sharing hardware architecture for deblocking filter. This architecture utilizes four edge filters to filter two edges of the 8 × 8 block in parallel. The edges are filtered following the sequential filter ordering. The proposed architecture is implemented in Verilog HDL and synthesized using Synopsys DC. The simulation results show that this architecture can process a 16 × 16 block in 45 clock cycles and hence an LCU in 720 clock cycles. It utilizes an area of 93.5 K in 32 nm technology supporting UHD video which is suitable for real-time applications.

Reducing parasitic coupling components can improve switching performance in electric circuits. A two-stage gate driver and power Gallium Nitride High Electron Mobility Transistors (GaN HEMT) were monolithically integrated for MHz-switching. The monolithic integration improves switching performance owing to minimized parasitic inductance. The proposed GaN-IC was fabricated using an enhancement-mode GaN-on-Insulator process technology. Experimental results showed that the GaN-IC had faster transition and less energy loss than a conventional circuit using a discrete gate driver. The proposed GaN-IC reduced switching time by 86% at turn-off and by 45% at turn-on under off-state V_DS of 100 V and on-state I_D of 10 A.

This paper presents a compact tunable tri-band filter with independently controlled passbands and high selectivity. The filter is comprised of three pairs of varactor-loaded λ/4 short-circuited resonators. Each passband of the filter can be independently tuned by varying the voltage applied to the corresponding resonators. In addition, a source-load coupling structure is employed to produce transmission zeros (TZs) achieving high selectivity. A prototype tunable tri-band microstrip filter is implemented. The experiment results show that the three passbands have tuning ranges of 0.81–0.99 GHz, 1.34–1.54 GHz, and 1.8–2.03 GHz, respectively.

A capacitor digital-to-analog converter (CDAC), which boosts the common-mode voltage and controls the input voltage rang, is proposed to improve the dynamic range and linearity of a single-ended successive approximation register (SAR) analog-to-digital converter (ADC). The 10-bit 10-MS/s single-ended asynchronous SAR ADC using the proposed CDAC is implemented by using a 180-nm CMOS process with a supply voltage of 1.8 V. Its active area and power consumption are 0.207 mm² and 2.29 mW, respectively. The measured DNL and INL are +0.93/−0.51 LSBs and +0.61/−0.81 LSBs, respectively. The measured ENOB is 9.04 bits for the analog input signal with Nyquist frequency.

We present in this paper an ultra-small plasmonic optical diode, which converts a symmetric mode into an asymmetric one and reflects backward propagation of the symmetric one, with a metal-insulator-metal (MIM) structure. A profile of an optical diode is derived from a topology optimal structure obtained in our previous study, and it is simplified so as to reduce insertion loss and difficulty in fabrication. An optimal profile is found out using a differential evolution (DE) which is one of the evolutionary algorithms, and optimization is carried out taken into account fabrication tolerance. According to the results of numerical simulation by 2D finite element method (FEM), the optimized plasmonic optical diode has insertion loss of <0.5 dB, reflection of <−20 dB in the forward propagation, and backward transmission of <−20 dB over C-band, and it is tolerant of ±5 nm boundary deviation. In addition, this device has an extremely small functional region (<1.5 µm).

A compact wideband fully tunable filter is designed based on a quarter-mode integrated waveguide resonator. With only two varactor diodes at the port gap, the notch frequency can be tuned continuously in the entire passband range, and the interference signal in the band can be flexibly suppressed. In addition, by controlling the on and off of two PIN diodes, switching between the two bandwidths of 1.7 GHz and 3.3 GHz is achieved without affecting the notch frequency tuning in the bandwidth. The notch frequency tuning range is 4 GHz to 6.4 GHz. The insertion loss at the notch frequency is −15 dB to −30 dB, which is sufficient to eliminate in-band noise.

This paper presents a new Gain-Adder (GA) circuit for Current-Reuse (CR)-RGC TIA. The proposed GA circuit employs one transistor alone to enhance bandwidth and decrease power consumption. The proposed CR-RGC TIA circuit is designed in a 65-nm CMOS technology. The simulation results confirmed that the proposed CR-RGC TIA circuit improves bandwidth by 83% and decreases the power consumption by 34% in comparison with the conventional one.

In this letter, a novel 3-D empty substrate integrated waveguide (ESIW) phase shifter with equal length has been proposed. The vertical transitions have been introduced into 3-D ESIW phase shifter in the propagation path. Based on it, the different total lengths of phase shifters in the propagation path and the equal total lengths of phase shifters in the external structure are compatible. The phase shifter consists of multi-layer PCB: top layer, interlayer, middle layer, ESIW PCB, and bottom layer. The theory and design process of ESIW phase shifter have been explained and discussed in detail. To demonstrate its feasibility, the 3-D ESIW phase shifters with equal external length are designed, manufactured and measured. Final results show that the phase shifts of 45.2° ± 3.7° and 89.7° ± 4.7° can be achieved over the entire Ka-band. Besides, the return losses and the insertion losses are better than 12.5 dB, and 1.9 dB, respectively.