A low critical path delay structure for composite field AES S-box based on constant matrices multiplication merging

抄録

In this paper, a low critical path delay (CPD) circuit structure is proposed for composite field S-box circuit. In the low CPD structure, multiplicative inverse over GF(2⁴) and multiplicative over GF(2⁴) are constructed by AND-XOR-networks. The XOR-networks in the last two multiplications over GF(2⁴) are further merged with the following constant matrix multiplication operation to shorten the CPD. Finally, hardware complexities of our designs are compared with previous works. The comparisons indicate that our proposed method is effective. Our design of S-box/InvS-box based on the proposed method has lower CPD.