2022 Volume 19 Issue 12 Pages 20220201
This paper proposed a digital synthesizable GMSK receiver baseband circuit for the Sub-GHz transceiver. The proposed digital baseband (DBB) circuit is composed of carrier recover, timing recovery, and demodulation blocks. An improved polarity Costas-loop with integration and dump (IP) is proposed for carrier frequency recovery. Timing recovery is based on the interpolation and Gardner error detection methods to determine the optimal sampling time. The proposed DBB is fabricated in 65nm CMOS technology. It realizes less than 10-6 bit error rate(BER) at 14dB Eb/N0 environment, with 314µW power consumption in the measurement.