A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits

抄録

In-situ timing monitor is widely used in the adaptive voltage scaling (AVS) system to eliminate the excessive design margin preserved for PVT variation. However, most of them suffer from the short-path (SP) issue where SPs must be padded to exceed the speculation window, incurring significant area overhead. A new in-situ timing monitor based on timing-error prediction is proposed in this paper, which can monitor the timing of the circuit across a wide voltage range. The SP issue is resolved by an SP isolation unit, and the speculation window is carefully determined to guarantee accurate timing-error prediction. A lightweight 13-T transition detector (TD) is designed to detect timing violations of critical paths. Furthermore, the proposed method is APR-friendly to EDA tools. All the proposed techniques are implemented in a CORDIC chip for demonstration targeting the SMIC 55nm CMOS process. Results show that the whole design achieves up to 53.2% energy saving with 6.1% area overhead as compared to the typical margined baseline circuit.