Sampling circuit issues in A/D converters and challenges for the solution

Abstract

This paper discusses issues of sampling circuits in analog-to-digital converter (ADC) and reviews some papers describing challenges for the solution to this fundamental issue of ADC. The energy consumption of the ADC is essentially determined by the capacitance. The peak current of the input signal sampling circuit is about 10 times larger than that of the continuous-time (CT) circuit and increases with resolution and conversion frequency. A CT-pipelined ADC using an analog delay circuit has been proposed to address this issue. Noise in the sampling circuit has been considered unavoidable and large capacitance has to be required to suppress the noise, but it has been shown that noise can be suppressed by placing an amplifier in front of the sampling circuit and changing the position of the sampling timing.