Parallel prediction methods for display stream compression encoder

抄録

The P-mode is the bottleneck restricting the DSC encoder’s encoding rate to 1pixel/clock. To enhance encoding efficiency, we improve the MMAP algorithm of DSC, then present a parallel P-mode circuit design based on the algorithm that enables processing 3 pixels in parallel. The algorithm test result indicates a marginal decline in PSNR by 1.15%. The synthesis result reveals that the circuit achieves 2.92 times the efficiency of the serial P-mode circuit we designed, with a 32.29% increase in area and 41.80% in power consumption, or about 1.14 times the efficiency of the DSC encoder chip at 0.38 times frequency.