IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE
Xiaoyue HuFangxu LvMingche LaiZhang LuoQiang WangChaolong XuRuotian YinZhouhao YangCewen Liu
著者情報
キーワード: equalizer, duobinary, PAM4, FFE, HPDFE, FPGA
ジャーナル フリー

2024 年 21 巻 19 号 p. 20240417

詳細
抄録

The proposed equalizer introduces a dual-mode structure that can be utilized for decoding four-level pulse modulation (PAM4) and duobinary (DB) signals. The DB modulation is achieved by combining the NRZ signal output from the channel with continuous time linear equalizer(CTLE). Using feed forward equalizer (FFE) and hybrid parallel decision feedback equalizer (HPDFE) for equalization and decoding in digital signal processor (DSP). Test results based on analog-to-digital converter (ADC) and FPGA verification platform demonstrate that the proposed design is Of great significance for implementation. 28G@-43dB nyquist channels are supported without a forward error correction (FEC) bit error rate (BER) of 1e-12 at 56Gb/s.

著者関連情報
© 2024 by The Institute of Electronics, Information and Communication Engineers
前の記事 次の記事
feedback
Top