The existing chip RF conduction immunity modeling method, integrated circuit immunity model conducted immunity (ICIM-CI), in mixed analog-digital integrated circuit (MADIC) is restricted by insufficient model nonlinearities, including large deviations between predictions and actual circuit performance under specific conditions, and the inability to carry out cascade quantization sensitivity simulations. This study presents an improved ICIM-CI modeling method, called ICIM-CI (nonlinear immunity behavior-NIB), which incorporates the concept of poly-harmonic distortion (PHD) to account for the conduction sensitivity of ICIM-CI in MADIC. This novel approach involves introducing multi-harmonic nonlinear coefficients into the immunity behavior (IB) module of the conventional ICIM-CI model, resulting in enhanced nonlinear characteristics of the IB module. The conventional ICIM-CI model can be improved from a binary judgment result model to a cascade simulation model with a nonlinear quantized output response. The proposed method can generate a broadband model on the conduction immunity of the chip in the frequency domain, and it supports cascade simulation. Measurements on a standard chip showed that compared with the traditional ICIM-CI method, the normalized root-mean-square error of this method is improved by 18.5dB, while the modeling time is reduced by about 98%.

In order to realize output power stabilization and reactive power minimization under possible coils misalignment occasion, a wireless power transfer system with improved primary modulation strategy and switch-controlled-capacitor (SCC) structure is proposed. The main contribution is that mutual inductance and primary self-inductance value can be estimated accurately via only virtual value of primary voltages and currents. No bulky auxiliary circuit, wireless communication, complex calculation and strict waveform quality is needed during the estimation process. Then according to the estimation result, a SCC structure and attendant control strategy is adopted to maintain the reactive power minimization. Besides, an improved primary phase shift (PS) modulation is proposed to realize the output power stabilization and enhance the system transmission efficiency. Finally, an experimental platform is built to verify the feasibility of proposed method.

In this letter, a design method of ultra-wideband power amplifier (PA) with multi-paths (MPs) impedance matching structure is proposed. MPs with unique impedance matching structure is combined with extended continuous Class-F (ECCF) theory to achieve ultra-wideband. Each path is responsible for the impedance matching of the specified band and apply to the input matching network (IMN) and output impedance matching network (OMN). To verify the proposed structure, an ultra-wideband PA is designed and fabricated by using CGH40010F. The PA operates over a multi-octave band from 0.5-4.3GHz, corresponding to the fractional bandwidth of 158.3%. This circuit provides drain efficiency (DE) of 57.7-77.2% and the output power between 39.4-42.2dBm over the operating band.

This paper presents a Quadrature Charge-Sampling Phase Detector PLL (QCSPLL) with low jitter and low reference spur. To address the issues of phase detection gain ambiguity and prolonged re-lock time in sub-sampling PLL, this paper employs a quadrature signal charge sampling gain compensation technique. A phase detector design that utilizes charge sampling and master-slave sampling is adopted, which achieves low reference spur while maintaining low in-band noise. QCSPLL uses a divider to provide four-phase signals. The divider also replaces the VCO buffer while generating the four-phase signal. QCSPLL is realized using a 28nm CMOS process. Simulation results show that the proposed QCSPLL has advantages in re-lock time. The re-lock time is improved by 63%. The prototype achieves 123-fs RMS jitter (10K-100M), -62.4dBc reference spur (without VCO buffer) and -255.2dB FoM.

This study investigates the influence of parasitic parameters in high-frequency PCB transformers (HFT(PCB)) on the performance of single-ended resonant aerospace DC/DC converters. An interleaved winding high-frequency PCB transformer, IW-HFT(PCB), was designed and compared with conventional HFT(PCB) in terms of power MOSFET voltage stress, output efficiency, and transformer operating temperature. A 100W aerospace DC/DC converter prototype was developed for validation, demonstrating significant improvements in current density distribution, magnetic field uniformity, reduction of leakage inductance, and thermal management with IW-HFT(PCB). The IW-HFT(PCB) design increased the maximum DC/DC output efficiency by 1.35% and full-load output efficiency by 1.33%. Moreover, peak voltage stress on power MOSFETs was reduced by up to 51.35%, while transformer temperature decreased by 3.9 degrees Celsius.

This paper presents the dual-mode waveguide loaded air slots resonator (DM-WLASR) that can exhibit a non-degenerate mode feature. That is, there is almost no coupling between the dual-modes. As a result, either mode could be the fundamental mode by adjusting the resonator dimensions, enabling a straightforward control of places of transmission zeros (TZs). Two second-order filters were designed for validation, each of which produces one TZ below/above the passband. Then the DM-WLASR cascades two coaxial resonators to form the novel “box section” topology. As an improvement, for the first time, the proposed topology could generate three TZs by introducing mixed-coupling and cross-coupling. In summary, all filters developed in the work provide the advantages of adjustable TZs and compact configurations. For fast demonstration, 3D metal printing technology was employed to manufacture the four-pole filter, and the tested results agreed well with the simulated results.

The proposed equalizer introduces a dual-mode structure that can be utilized for decoding four-level pulse modulation (PAM4) and duobinary (DB) signals. The DB modulation is achieved by combining the NRZ signal output from the channel with continuous time linear equalizer(CTLE). Using feed forward equalizer (FFE) and hybrid parallel decision feedback equalizer (HPDFE) for equalization and decoding in digital signal processor (DSP). Test results based on analog-to-digital converter (ADC) and FPGA verification platform demonstrate that the proposed design is Of great significance for implementation. 28G@-43dB nyquist channels are supported without a forward error correction (FEC) bit error rate (BER) of 1e-12 at 56Gb/s.

This paper presents a highly independent quad-channels 2^nd order diplexer for 5G and Wi-Fi applications. The proposed diplexer was developed by utilizing four overlapped modified open-ended rectangular resonators (MOERRs). The OERRs of both applications were loaded in parallel to a microstrip feed line in order to reduce the diplexer size and enhance the isolation level. The minimum measured insertion loss for the operating channels were 1.962dB, 2.941dB, 1.925dB, and 2.397dB with center frequencies of 3.586GHz, 4.143GHz, 5.193GHz, and 6.135GHz, respectively. Moreover, the measured return loss were better than 20dB and the isolation at the operating bands were better than 23.13dB. The measured results validated the simulated findings with small variations that mainly attributed to fabrication and material uncertainty.

The parasitic thyristors inside the SiC IGBT are accidentally turned on, resulting in a sharp increase in the anode current. The continuous high current and out-of-control state may cause permanent damage to the SiC IGBT device, affecting the stability and safety of the entire circuit. In this paper, the static latch-up effect of SiC IGBT is deeply studied based on the Sentaurus TCAD simulation platform. By adjusting the key parameters such as drift region thickness and buffer thickness, the influence of different structural parameters on the latch-up effect of SiC IGBT is analyzed. Three structures of SiC IGBT including N+ emitter ballast resistance, shallow P+ injection, and deep P+ injection are simulated to suppress the latch-up effect. The simulation results show that these three structures can suppress the latch-up effect of SiC IGBT to a certain extent. Among them, the structure with deep P+ injection has a stronger anti-latch-up ability and larger anti-latch-up threshold, and the on-state voltage drop of the control device is unchanged while the turn-off loss is reduced. The structure of deep P+ injection provides a certain reference for improving the performance and reliability of SiC IGBT.

The Single-event Transient (SET) pulses triggered at the drain of NMOS with T-gate at various striking positions after heavy-ion striking are studied using Technical Computer Aided Design (TCAD) simulation based on the 130nm Fully Depleted Silicon on insulator (SOI) technology. Based on this technology, we design Flip-Flop chain circuits with different gate widths and gate lengths. The heavy ion irradiation experiment of the device is carried out.

Three-dimensional (3D) integration based on through silicon via (TSV) is one of the most promising technologies in the post-Moore Era. However, increased power density will cause great challenge in heat dissipation and affect the reliability of 3D integrated systems, especially 3D power integrated systems. Except for signal connections, TSV can also be used as thermal conduction pathway. An embedded heat dissipation structure with different size TSVs in different layers of power chips is proposed in this paper. The radius of TSVs in the lower dies is larger than that in the upper dies. Numerical investigation indicates that, compared with the embedded heat dissipation structure with uniform TSV, the proposed structure with the radius of TSVs from top to bottom is 11µm, 20µm, and 23µm, can significantly improve the cooling capability. The volume of heat sink of the proposed structure is much smaller than that of two-dimensional structure. Increasing the number of internal fins has improved heat dissipation effect for the proposed structure.

In wireless power transfer system, the frequency splitting phenomenon occurs due to over-coupling and low impedance loads, which lead to reduced transmission power. This letter proposes a method using series-connected variable inductors (VIs) on both primary and secondary sides to avoid frequency splitting under fixed frequency condition, while zero voltage switching and zero current switching can be realized over a wide range Lastly, a 100W experimental prototype was constructed, and results indicate that at a fixed input voltage of 50V, the system achieves an efficiency of 87.3%. In comparison to the condition of FSP, the input power shows a 336% improvement, rising from 22.9W to 99.3W.

This paper presents a 1.25-GS/s 14-bit pipelined analog-to-digital converter that employs two linearity improvement schemes. A current-feedback flipped input buffer is proposed, which can effectively mitigate the effect of non-linear parasitic capacitances, sampling circuits, and finite output impedance of tail current sources on linearity. Additionally, most of the non-linearity in the ADC core is improved by implementing the large dither injection. The proposed input buffer is designed in a 40-nm CMOS process under a 2.5-V supply voltage. The simulation results show the input buffer can achieve SFDR > 80.1dBc and SNDR > 70dB with a power consumption of 65mW at 1.25-GS/s for input signal frequencies less than 1.5-GHz. The SFDR of this ADC can be improved by about 3.5dB by using large dither technique. The entire 14-bit ADC achieves a 65.6dB SNDR and a 78.1dBc SFDR at 1.25-GSps while the core of ADC consumes 510mW, achieving a FoM_w of 262.8fJ/conversion-step.

Non-volatile memory (NVM) technologies (e.g., phase change memory (PCM), magnetic random access memory (MRAM), etc) are projected to be able to provide higher capacity with lower cost than DRAM in the near future. Accordingly, recent researchers are attempting to construct heterogeneous memory systems by combining NVM with DRAM to overcome the disadvantages of DRAM. However, the different characteristics of NVM and DRAM pose a major challenge, which carefully places the data in the appropriate memory without the requirement of disruptive change to applications as far as possible. In this paper, we propose a compiler-assisted data placement technique for heterogeneous memory systems, including NVM and DRAM. Our scheme exploits the features of the compiler to enable data placement without the modification of applications or the OS. With the assistance of the compiler, we collect information (e.g., memory usage) for dynamic placement and allocation of data objects between NVM and DRAM based on the information. We implement our scheme in a Low Level Virtual Machine (LLVM) compiler infrastructure and evaluate its performance in real systems by injecting NVM latency using Quartz. In the experimental results, we demonstrate the effectiveness of our scheme for different memory configurations.

The body diode characteristics at high di/dt (approximately 2000A/µs) were evaluated for four power devices with a breakdown voltage of 650V: (1) GaN-FET (cascode), (2) SiC-MOSFET, (3) Si-SJ-MOSFET, and (4) Si-RC-IGBT. The Qrr of the GaN-FET and SiC-MOSFET were approximately 6.3% and 4.5% of that of the SJ-MOSFET, respectively. The GaN-FET has a cascode-connected Si-MOSFET body diode. The accumulation of minority carriers in this diode was small, and the main component of the recovery current was due to the parasitic capacitance of the device. In addition, in the IGBT, a dynamic avalanche occurred and a second peak appeared in the recovery current.

A phase-locking system is designed and developed to measure and compensate for the phase fluctuations in real time at an intermediate node. The performance of the compensated feedback loop is theoretically analyzed and simulated. Radio frequency generators and mixer emulate the lasers and interference plus photon counting processes to perform closed-loop verification without lasers. When the sum of the linewidths of the two emulated lasers is 1.175kHz, the interference root-mean-square phase noise is suppressed from 1626° to 30°. A closed-loop phase noise of approximately 13° is expected for field experiments with the same laser linewidth and 8µs loop delay.

Linearity testing of an analog-to-digital converter (ADC) with automatic test equipment is expensive and challenging. In this paper, an improved method is proposed for high-precision ADC linearity testing to substantially relax the stimulus linearity requirement and reduce the test time. Two nonlinear but functionally related input signals are used as the ADC excitation, and a stimulus error removal technique is used to obtain the test results. This method makes it possible to test the static parameters of high-resolution ADCs by using low-precision ramp signals with fewer sampled points. Compared to the histogram method, the proposed method can save 90% of the test time to achieve the same accuracy. Simulation and measurement results demonstrate the functionality and robustness of the proposed method.