A high performance NVMe host logic engine based on dynamically configurable queues and co-design of NVMe and PCIe

抄録

Aiming at the demand for FPGA-based high-bandwidth NVMe SSD host access, this letter presents an NVMe over PCIe Hardware Acceleration Engine (NoPHAE), which has two innovative aspects. Firstly, an NVMe Queues Engine is integrated into the NoPHAE to enhance I/O performance and reduce resource consumption. The NVMe Queues Engine provides dynamic queue configuration and introduces a virtual completion queue, which reduces resource consumption by 20%. Secondly, a PCIe Acceleration Engine is built in the NoPHAE, which implements the co-design of PCIe and NVMe and optimizes the timing for processing PCIe transport layer transactions, resulting in a significant increase in data throughput. Test results indicate that the sequential read and write speed of the NoPHAE is 7.93 times faster than that of the baseline, and the random read and write performance is two times faster than that of the baseline.