MiniRV: A subcompact RISC-V core with optimized instruction set for chiplet system

抄録

In current multi-core systems, the MCU typically employs a full instruction set, but only a limited subset of instructions is actually utilized, leading to wasted area and power consumption. This study presents the design of a RISC-V-based coprocessor, MiniRV, aimed at improving resource utilization in multi-chiplet systems, reducing both area and power consumption while maintaining task execution efficiency. The coprocessor features a three-stage pipeline structure, enabling simplified design and minimal area occupation. A dedicated compiler was also developed to support its instruction set. The validation results show that, compared to PicoRV32, MiniRV reduces area by 43.14%, power consumption by 38.86%, while the code execution efficiency remains unchanged.