An application dependent FPGA interconnect testing scheme is presented. The goal is to reduce the number of test configurations while keeping high fault coverage. Reduction is done by using SMT constraints that allow multiple nets as a group to use one input vector, so that the number of test configurations is reduced. Based on the complete fault model, a novel approach to generate SAT formulas, most notably dominant bridging faults, is explained to retain coverage. Experiments on FPGAs shown that this method yield on average 23.5% fewer configurations on circuits with 1000~70000 LUTs comparing with existing methods, with full fault coverage.

Low-offset operational amplifiers are widely employed in readout circuits. Conventional calibration techniques such as chopper or fuse trimming face the inherent contradiction between repetitive calibration and small area and power consumption. Memristors offer a promising alternative with their unique characteristics of continuously variable resistance, repeatable programmability, and compact size. This paper proposes a memristor-based multiple-time adaptive trimming circuit for amplifier offset. A folded cascode two-stage operational amplifier was fabricated using the 180 nm CMOS process and trimmed by the proposed technique. Chip testing demonstrates that it reduces amplifier offset voltage to below 57.8 μV level while occupying only 1829 μm² of circuit area, providing a new low-cost feasible approach for repeatable offset compensation.

As advancements in power integrated circuit design and semiconductor technology continue, motor drivers are evolving toward smart power integrated circuit (SPIC). This paper presents the design of a high-voltage, two-phase stepper motor driver chip based on a 0.18 μm BCD process. The driver integrates several key modules, including a low-voltage power module, current sensing module, charge pump module, driver circuit module, and protection module. To improve system stability and precision, two sets of cascode current mirrors are employed to sample the H-bridge current. Test results demonstrate that the chip can reliably operate within a supply voltage range of 8 V to 40 V, achieving a maximum current output of 2 A and a continuous drive current of up to 1.6 A. Furthermore, the chip exhibits stable current steps with each stepping pulse.

In current multi-core systems, the MCU typically employs a full instruction set, but only a limited subset of instructions is actually utilized, leading to wasted area and power consumption. This study presents the design of a RISC-V-based coprocessor, MiniRV, aimed at improving resource utilization in multi-chiplet systems, reducing both area and power consumption while maintaining task execution efficiency. The coprocessor features a three-stage pipeline structure, enabling simplified design and minimal area occupation. A dedicated compiler was also developed to support its instruction set. The validation results show that, compared to PicoRV32, MiniRV reduces area by 43.14%, power consumption by 38.86%, while the code execution efficiency remains unchanged.

We have applied the symplectic integrator (SI) scheme based on the fast Fourier transform, namely, FFT-SI, to electromagnetic field analysis for inhomogeneous and dispersive media. The auxiliary differential equation (ADE) for chromatic dispersion was formulated along with the time-dependent Maxwell equations. We examined two distinct dispersion models for ADE: one based on Sellmeier equation and the other based on the Lorenz-Drude model. Our computational results for one-dimensional problems were compared with exact solutions to examine numerical accuracy with respect to the time and space step sizes, allowing us to assess applicability of higher-order algorithms and effects of numerical dispersion errors. Extension of the present computational method for two-dimensional problems used for application development was also examined.

This letter presents a high-linearity input buffer for RF sampling ADC. A common-source operational amplifier is added as a bootstrap circuit to mitigate the influence of channel-length modulation and current extracted by sampling circuits. A cross-coupled substrate technique is introduced to enhance the output impedance of tail current sources, thereby further improving linearity. The proposed input buffer is designed using a 40-nm CMOS process, consuming 60-mW under a 2.5-V supply, which can be applied in a 1.5-GS/s 14-bit pipelined ADC. Simulation results demonstrate that the input buffer achieves an SFDR/SNDR of 80.3/69.2 dB with a 1283-MHz input at 1.5-GS/s.

This paper proposes an analog front-end circuit applicable to single-lead ECG signal acquisition based on a 0.18 um process. The circuit employs an AC capacitive coupling instrument amplifier (ACIA) with a DC servo loop, significantly improving input impedance. Simulation results indicate an input reference noise of 8.538 uVrms, an ECG signal voltage amplification factor of 30 V/V to 240 V/V, and an input impedance of 4.59 GΩ @15 Hz. The circuit also features low input noise and a high common-mode rejection ratio of 114 dB.

In this study, we proposed a low-cost and simplified method for detecting blood vessels in fat using high-frequency current during surgery. Conventional methods for detecting blood vessels are not often used in surgery because they are complex systems to detect blood vessels for surgeon. In this paper, we calculated the real and imaginary parts of impedance between two electrodes inside the presence and absence of blood vessel in the fat in kHz band. Based on the results, we could find the possibility of blood vessel detection in the fat by impedance change.

Based on the study of the influence of the air gap length on the core characteristics, a method to determine the optimal air gap length of the core is proposed for energy harvesting of transmission lines. The equivalent model of the core is established, and the relationship between the optimal air gap length and the saturation primary current is derived. The simulation and experimental results show that when the air gap does not exceed 5% of the length of the magnetic circuit, the saturation characteristic model established in this paper can accurately calculate the optimal primary current with a calculation error of less than 5%. The air gap length corresponding to the optimal primary current is the optimal air gap length, and at the optimal air gap length, the core output efficiency is close to maximum, which has specific engineering utility value.

This study presents a W-band antenna integration module using High-Density Interconnect (HDI) technology for radar applications. The module integrates 64 transmit/receive (TRX) channels, each with a 2×2 sub-array, forming a 16×16 antenna array. To address warpage and manufacturing constraints caused by asymmetric copper coverage in HDI substrates, we introduce non-resonant patches and cavity structures, enhancing copper uniformity and gain performance. Broadband impedance matching techniques mitigate vertical impedance discontinuities. A single TRX channel demonstrates a 23.35% impedance bandwidth (87-110 GHz) and a peak gain of 13.74 dBi. The full module’s simulated peak gain reaches 26.83 dBi at 97 GHz, confirming the viability of HDI technology for W-band antenna integration.

Nowadays, Frequency-Modulated Continuous Wave (FMCW) radar systems are widely used. These radar systems usually suffer from undesired patterns include the interference from transmitter or LO, multiple reflections of static objects in the environment. Traditional baseband processing uses high-pass filters (HPF) to suppress these interferences; however, HPFs have both slow settling due to low cut-off frequency, and attenuation to real objects reflections at near frequency band. Some studies have tried to cancel the interference actively, however additional cancel errors are induced. In this paper, a novel active cancel methodology is proposed with pattern cancel DAC and remove the cancel error with feedforward compensation. It is verified on silicon to be effective to mitigate the interference and enhance the linearity of the FMCW baseband greatly.

This letter presents a 5.2-6.4 GHz fractional-N phase-locked loop (PLL) with low in-band fractional spurs. The proposed probability-distribution-shaping delta-sigma modulator (PDS-DSM) reduces the in-band fractional spurs arising from loop nonlinearity by changing the probability distribution of the DSM. The enhanced PDS-DSM is realized by integrating the PDS dither with a multi-mode filter at the output stage of a conventional MASH 1-1-1 architecture. The proposed PLL was fabricated in a 65 nm CMOS process. Notably, with the incorporation of second-order and third-order filtered PDS dithers in the PDS-DSM, in-band fractional spurs at 10 kHz offset from 5.825 GHz were reduced from -49.5 dBc to -58.2 dBc and -62.8 dBc respectively.

This paper presents a high-linearity millimeter-wave (mmWave) Doherty power amplifier (PA) for 5G FR2 wireless communications. A precise mutual distortion cancellation (PMDC) method for parallel Doherty PA is proposed. The auxiliary path current amplitude is adjusted by the common-source common-gate (CSCG) dual adaptive bias circuit (DADB). Meanwhile, the main path current phase is tuned by the phase nonlinear compensation capacitor (PNCC). These two techniques are combined to enable precise distortion cancellation, thereby optimizing the Doherty PA’s AM-AM and AM-PM distortions. The chip is fabricated in a 40 nm CMOS process. The measurement results show that the proposed Doherty PA achieves a small-signal gain of 19.6 dB, a 3-dB bandwidth from 21 to 29 GHz, a saturated output power (P_sat) of 19.1 dBm, an output 1-dB compression point (OP_1dB) of 17.9 dBm, a peak power added efficiency (PAE_peak) of 22.7%, a power added efficiency at 6-dB power back-off (PAE_-6dB) of 15.1%, and an AM-PM distortion of 0.93° at 26 GHz. When using a 64-QAM 100 MHz OFDM modulated signal as the input, which meets the 5G NR FR2 communication protocol and has an input PAPR of 11.38 dB, the measured output EVM is -25 dB, and ACLR is -30.5 dBc. The proposed PA realizes an average output power (P_avg) of 12.6 dBm and an average power added efficiency (PAE_avg) of 11.3%.

This study proposes a novel technique called the guided spontaneous emission circuit (GSEC) technique that can largely enhance the optical power resolution (OPR) of optical power variation measurement systems. The improvement factor (IF) in the OPR achieved by the GSEC technique is determined by the slope of the nonlinear optical input-output curve in dBm of the GSEC. Through experimental analyses, we clarified the characteristics of the IF and successfully optimized it by implementing a two-stage GSEC with two erbium-doped fibers (EDFs) and two optical filters. By optimizing the configuration of the two-stage GSEC, we achieved an optimized IF of approximately 30.6.

In this study, a generalized BLT equation based on EMT is proposed to predict the SE of the rectangular enclosure with complex apertures. Aperture structures are decomposed into rectangular units, with equivalent impedances computed using Robinson’s coplanar stripline model or Nie’s capacitive-inductive diaphragm model. The Robinson model considers the influence of eccentric apertures by introducing the aperture position factor and takes into account the high-order modal effect and the SE prediction from any observation point. The results show that the Robinson model performs better than the Nie model in the high-order modes, both of which are effective under the main mode conditions, and the Nie model is more adaptable to the aspect ratio of the aperture. The effectiveness of this method in SE prediction of the rectangular enclosure with complex apertures is verified by comparison with CST Studio Suite.

This paper proposes a novel low-voltage and high-linearity input buffer for high-performance Analog-to-Digital Converters (ADCs). The use of current feedback and an auxiliary source follower (SF) is crucial for enhancing linearity, reducing power consumption, and minimizing the circuit area. The proposed buffer, designed in a 40-nm CMOS process, achieves a spurious-free dynamic range (SFDR) exceeding 73.6 dBc at a 1 GS/s sampling rate with a 3.3 pF load capacitance. It occupies 0.00684 mm² and consumes 43 mW at 2.5 V, including bias and common-mode feedback (CMFB) circuits.

The edge electric field effect of the Schottky junction impacts the diode performance, limiting their application in terahertz frequency multiplier circuits. To address this problem, this paper presents a novel GaAs Schottky barrier diode (SBD) with a vertical sidewall epitaxial profile, which is fabricated by Inductively Coupled Plasmadry (ICP) dry etching. Electromagnetic simulation of the two types of SBD is also carried out to investigate the effect of structural changes on the parasitic effects. Compared to the normal structure SBD, the new design increases the reverse breakdown voltage from -7.5 V to -8.4 V and reduces the coupling capacitance between the metal finger and the mesa from 4.9 fF to 1.7 fF. A 170 GHz frequency doubler based on this diode demonstrates a maximum frequency doubling efficiency improvement of 4.9% over normal structure SBD, which validates the effectiveness of the SBD with a vertical sidewall epitaxial structure in enhancing the performance of frequency multipliers.

This study investigates the amplitude noise suppression of 20-Gbit/s quadrature phase-shift keyed phase-conjugated twin waves (PCTWs) by frequency non-degenerate phase-sensitive optical amplification. The amplitude fluctuations of PCTWs are converted into phase fluctuations through the optical Kerr effect in transmission optical fibers. The average phases of transmitted PCTWs are then phase-locked to the pump phase and subsequently phase-rotated by an appropriate amount. This sequence results in amplitude noise suppression through optical parametric processing when the appropriate phase rotation is applied. Numerical simulations investigate the signal-to-noise ratio (SNR) of transmitted PCTWs with optical noise simulating the noise conditions of multi-relay transmissions, in a single-span transmission model. The SNR improvement is observed irrespective of whether the optical noises between PCTWs are correlated or not.

This paper designs a perovskite-metal hybrid metasurface that can independently control the phase of transmitted and reflected waves under the same incident terahertz wave, thereby achieving different wavefront functions in different electromagnetic spaces. The designed metasurface has two layers of perovskite-metal and one dielectric layer. When the perovskite is in metallic state, the metasurface works in transmission mode; when the perovskite is in insulating state, the metasurface works in reflection mode. By utilizing the geometric phase principle and the convolution principle, a four-focal-lens is realized in the transmission space, while generating a four-channel orbital angular momentum in the reflection space. This work offers potential applications in dynamic imaging, communication, and other fields.

The nonlinearity of optoelectronic devices is critical in broadband systems due to harmonic and intermodulation interference. This study proposes a method to evaluate second- and third-order nonlinearities in photodetectors using optical two-tone signals with wide frequency separation. Two models address frequency-dependent effects, with corrections for accurate measurement. Experiments with amplifiers and passive components validated the approach. The method enables reliable performance evaluation of optical devices, contributing to low-distortion, high-speed optical communication systems.