Adder-free dynamic compensation for logarithmic multipliers based on minimum worst-case error

Abstract

Logarithmic multipliers offer hardware efficiency but suffer from significant errors. This brief proposes a high-accuracy design using a WCE-minimizing compensation algorithm that dynamically selects the larger operand for optimal scaling. The resulting compensation value enables direct error correction without additional adders. Zero-padding exploitation facilitates bit-width truncation, reducing barrel shifter and adder complexity while preserving accuracy. Compared to prior designs, the multiplier achieves minimal normalized mean error distance (NMED) and mean relative error distance (MRED) with near-optimal power-delay product (PDP), establishing an optimal accuracy-efficiency tradeoff. Additionally, it induces a double-sided error distribution that mitigates excessive error accumulation in multiply-accumulate applications.