An oscillator replica bitline technique for suppressing timing variation of SRAM sense amplifiers

Abstract

With advances in CMOS technology, the threshold voltage variation has worsened, which has a bad impact on the timing variation for sense amplifier enable signal. This paper proposes an oscillator replica bitline (ORB) technique for suppressing timing variation of SRAM sense amplifiers. The number of MOSFETs used in the ORB technology is approximately 40% of that in conventional replica bitline technique and the ORB technique can be programmed to modify sense amplifier enable timing. The simulation results show that, at a supply voltage of 0.8 V, the timing variation can be reduced by approximately 52.37% and 6.29% compared with the conventional replica bitline technique and replica bitline with multistage technique, respectively.