A 0.75 µA-quiescent current, output capacitor-less LDO regulator with high power supply rejection

Abstract

This paper presents an output capacitor-less LDO regulator (OCL-LDO) with high PSR and ultra-low quiescent current. The circuit utilizes a local feedback amplifier based BGR and a pseudo-dynamic biased error amplifier to improve its PSR. Hereinto, the modified super source follower solves the stability problem in the local loop and further reduces the output impedance. Furthermore, the nested miller compensation based on dynamic nulling resistor (DNR-NMC) is utilized to keep stable in the full load range. The transient enhancement circuit can reduce the overshoot and outshoot voltage by 68% and 35%, respectively. This design implemented in 180 nm technology occupies an area of 0.132 μm² and provides a controllable output over a supply range of 2.5 V-5 V and the maximum output current is 100 mA. The PSR is less than -75 dB at 100 Hz and -40 dB at 10 kHz with the load current of 100 mA. Additionally, the line regulation and load regulation are 0.08%/V and 0.21%/A, respectively.