抄録
This paper presents the design of a 6-bit active digital phase shifter in 0.18-µm CMOS technology. The active phase shifter synthesizes the required phase using a phase interpolation process by adding quadrature phased input signals. It uses a new quadrature all-pass filter for quadrature signaling with a wide bandwidth and low phase error. The phase shifter has simulated RMS phase error of <0.85° at 2.4-5GHz. The average voltage gain ranges from 1.7dB at 2.4GHz to -0.14dB at 5GHz. Input P1dB is typically 1.3±0.9dBm at 3.5GHz for overall phase states.
