IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Thermal and competition aware mapping for 3D network-on-chip
Bixia ZhangHuaxi GuYintang YangKun WangZhengyu Wang
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ジャーナル フリー

2012 年 9 巻 19 号 p. 1510-1515

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抄録
Three-dimensional network-on-chip (3D NoC), which combines NoC with 3D IC technology, offers several prominent advantages, including reduced overall interconnection length and design flexibility. However, it suffers from the high chip temperature problem. In the ciliated 3D Mesh architecture, the competition for the port of the router is fierce. A new temperature and network competition-aware mapping algorithm is proposed to reduce the peak temperature and decrease the network competition. The new algorithm can realize the multi-objective mapping and ensure a lower time complexity. Simulation results show that our method achieves an appropriate balance between peak temperature and network competition.
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© 2012 by The Institute of Electronics, Information and Communication Engineers
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