2012 Volume 9 Issue 23 Pages 1775-1779
In scaled technologies, large cell-to-cell interference and F-N tunneling disturbance degrade threshold voltage (Vt) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P1 ∼ P7) in the narrow Vt window, incurring large bit-error rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of Vt window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent Vt window sizes, the proposed technique provides 12.5∼18.4% smaller BER compared to conventional Gray-code mapping.