In scaled technologies, large cell-to-cell interference and F-N tunneling disturbance degrade threshold voltage (Vt) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P1 ∼ P7) in the narrow Vt window, incurring large bit-error rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of Vt window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent Vt window sizes, the proposed technique provides 12.5∼18.4% smaller BER compared to conventional Gray-code mapping.
A novel integrated single-inductor dual-output (SIDO) buck converter with peak current common-mode and the two output voltage ripples comparison differential-mode control method in continuous conduction mode is presented. The system can use only one inductor to provide two independent output voltages, 1.2V and 1.8V, with a maximum total output current 460mA. The proposed converter has been fabricated in a 0.18µm 1P6M CMOS process. Experimental results show the load transient response time is only 8µs and the cross-regulation is about 0.05mV/mA when the load current suddenly changes 200mA. The maximum power conversion efficiency 93.5% is achieved at total output power 240mW.
This paper presents a K-band Gilbert mixer in a 0.18µm CMOS technology by means of a π-Network and Post Distortion Cancellation (PDC) technique to achieve high gain, high linearity, and moderate noise figure. We use the parasitic capacitances that appear at nodes between RF and LO stage for implementing π-Network. Circuit analysis and MATLAB simulation show that the above technique is useful for wide-band applications. Simulation illustrates a power consumption of 9.68mW at 1.8V, 3.36dB improvement in power conversion gain, and 2dB reduction in NF at 21.5GHz with LO power of -1dBm in comparison with the case when PDC technique is used only. Compared to conventional mixer, it improves the IIP3 by 6dB.
The impact of carrier pulling on the modulation characteristics of a transistor laser is discussed. The results of a theoretical analysis of modulation bandwidth and damping effect show that the carrier transport effect obtained by using a transistor laser allows for a gain compression factor of about one-tenth that of a conventional laser (0.7×1017cm3), as well as for a maximum modulation bandwidth of 45GHz.
A human body can be considered as a communication channel in which the electrical signal propagates through the body based on an electrostatic coupling mechanism when the frequency is sufficiently low. Since the human body approximately acts as a conductor in this case, we can detect the existence of the human body by measuring the corresponding electric filed variation in a close proximity of the human body. In this study, we aim to detect the approaching direction of a human arm based on this electrostatic coupling mechanism in human body communication for application to a user-machine interface. We first provide an appropriate explanation of this detection system based on the electrostatic coupling mechanism, and then conduct not only a computer simulation but also an experiment to validate the feasibility of the proposed detection system.
A true single-phase clocked (TSPC) flip-flop, which compensates for the leakage current generated at dynamic nodes, is proposed to cover a wide operational frequency range in submicron CMOS processes. To implement the proposed TSPC flip-flop, three feedback circuits composed of a gated inverter (GI) are added to the conventional TSPC flip-flop. The GI is controlled by a clock and the internal signal of the conventional flip-flop, without an external control signal or a complementary clock signal. Furthermore, the strength ratio of the normal path to the feedback path does not need to be considered for the proposed TSPC flip-flop since the feedback circuit is only enabled when the dynamic node acquires a floating state. The proposed TSPC flip-flop is designed using a 1-poly 6-metal 65nm CMOS process with a 1V supply voltage. The simulation results show that the proposed TSPC flip-flop, which is optimized for normal operation at an operational frequency of 2GHz, exhibits an error-free operation at low operational frequencies such as 1MHz. The three added feedback circuits increase the power consumption by 8.8% as compared to that of the conventional TSPC flip-flop and occupy 12.28% of the proposed flip-flop.