In scaled technologies, large cell-to-cell interference and F-N tunneling disturbance degrade threshold voltage (V
t) window which we can place program states. Moreover, in
Triple Layer Cell (TLC) NAND Flash we should place seven program states (P
1 ∼ P
7) in the narrow V
t window, incurring large
bit-error rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of V
t window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent V
t window sizes, the proposed technique provides 12.5∼18.4% smaller BER compared to conventional Gray-code mapping.
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