抄録
Asymmetric monotonic switching scheme is proposed for a low power successive approximation register (SAR) analogue-to-digital converter (ADC). The proposed switching procedure consumes no energy from reference voltage for the first 3 MSB (most significant bit) conversion using unequal initial DAC setting and asymmetric binary search algorithm. After 3 MSB conversions, DAC switching utilizes a conventional monotonic DAC switching for further energy saving. As a result, average energy saving during conversion cycles has been improved up to 98.5% as compared with conventional architectures.
