論文ID: 14.20170668
This paper describes a low-power object recognition processor VLSI for HDTV resolution video at 60 frames per second (fps) using an object recognition algorithm with Sparse FIND features. The VLSI processor features two-stage feature extraction processing by HOG and Sparse FIND, a highly parallel classification in the support vector machine (SVM), and a block-parallel processing for RAM access cycle reduction. Compared to the accuracy by the original Sparse FIND algorithm, the two-stage object detection demonstrates insignificant accuracy degradation. Using this architectural design, a 60 fps performance for object recognition of HDTV resolution video was attained at an operating frequency of 130 MHz. This 3.35 × 3.35 mm2 chip, designed with 40nm CMOS technology, contains 8.22 M gates and 5Mb SRAM in the chip of 3.35 × 3.35 mm2. The simulated power consumption at 133MHz were 528mW and 702 mW at the slow process condition (SS, 0.81 V, -40°C) and typical process condition (TT, 0.9 V, 25°C), respectively.
