Design of a low-insertion-phase-shift MMIC attenuator integrated with a serial-to-parallel converter

抄録

This work presents a monolithic DC~4GHz 6-bit digital attenuator with low insertion phase shift and attenuation error. Based on GaAs E/D pHEMT process, a serial-to-parallel converter is introduced to decrease the control pads of the chip. In the 16dB attenuation bit, a switched-path-type topology is employed in order to extend the bandwidth and achieve low insertion phase shift. The attenuator has 0.5dB resolution and 0~31.5dB attenuation range. Measurement shows less-than-2.3dB insertion loss at reference state, and larger-than-14dB return loss at all states. An rms attenuation error of less-than-0.3dB and phase-shift-variations less than 2deg are achieved. The size of the chip is 2.0mm×1.7mm.