論文ID: 14.20171007
A third-order single-bit delta-sigma modulator is presented in this paper. An op-amp dynamic current biasing technique is used to improve the power-efficiency of the modulator. The voltage reference block is integrated with the delta-sigma modulator core to avoid the use of large off-chip bypass capacitors and to minimize pin numbers. It achieves 89.2 dB dynamic range over 10 kHz signal bandwidth with an oversampling ratio of 128. The delta-sigma modulator core and on-chip voltage reference block consume 880 μW and 550 μW, respectively, from a 1.8 V power supply. The prototype chip occupies 1.26 mm2 using a 0.18 μm CMOS technology.
