A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

Abstract

A synchronous driving approach for stitching CMOS image sensor is proposed. Dual row signal line driving architecture must be considered in the design of large array CMOS image sensor. However, as the size of the array increases further, the traditional synchronization technologies such as clock tree cannot be applied because of the stitch technology, Furthermore, this invalidity will cause DC shoot through and dead line. Based on the adaptive delay phase-locked loop, dual row signal line synchronous driver for pixel array is realized in a single die CMOS image sensor with 225M pixels and large area of 120×120mm². Timing matching improves by two orders of magnitude, and 99.95% consistency is achieved.