Recent advances in computer design allow microprocessors to enable parallelism in programs in order to achieve high performance. True dependency is one of the many factors that restrict parallelism in a computer program. To overcome the restrictions of true dependency, a number of schemes for value prediction have been proposed. The value predictor predicts an instruction result on the basis of the value history obtained from Value History Table (VHT). However, it consumes considerable energy because VHT is large and is referenced very frequently. In this paper, we propose a more efficient mechanism for a value predictor that extends the use of an existing branch target buffer (BTB) to reduce the number of invalid VHT references. We introduced a predictability bit (p_bit) to identify an instruction that has a predictable value, and we added a field to BTB to ensure that the p-bits corresponded to successive instructions. The proposed mechanism controls VHT references on the basis of p_bits. The evaluation results show that the proposed mechanism reduces invalid references by 27.6% and 42.4% and energy by 16.6% and 25.7% with 0.1% performance loss on average in the 8 and 32 p_bits length, respectively.