集積化マルチフェーズコンバータのチップ面積最小設計

抄録

Dynamic voltage scaling (DVS) is one of the most effective power reduction techniques for a digital VLSI circuit. A fully integrated DC-DC converter is indispensable to achieve DVS. There is a trade-off between the output voltage ripple of a fully integrated DC-DC converter and its chip area. This paper proposes a design methodology which minimize the total chip area of a fully integrated multi-phase converter with an acceptable voltage ripple. The proposed design methodology reveals an equation of the optimum inductance and capacitance. Validity of the proposed design methodology is confirmed by Hspice simulations. The simulation results of a design example show that the output voltage ripple of a multi-phase converter with the optimum inductance and capacitance derived by the proposed design methodology is kept within a requirement value.