抄録
We are studying an FPGA-based ASIC emulator via high-speed serial communication. In this emulator, there are restrictions on placement of the FFs on FPGA and we have to reduce the number of replicated logic gates and replicated input terminal when partitioning the cicuit to FPGAs. In this paper, we report a study of new circuit partition method using logic-corns. Compared with hMETIS, it achieved average 49.1% reduction in the method for suppressing the duplicution of external inputs. In the method for suppressing the duplicution of nodes, it achieved average 51.7% reduction.
