低消費電力チャージリカバリー論理回路構造の設計

抄録

A new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL) is proposed, fully powered by 2-phase alternating power clocks. Each CPBL gate consists of two parts working in mutually exclusive intervals. The performance and energy efficiency have been assessed through the 4-bit counter implemented in CPBL, CPAL and static CMOS with the same 0.18μm CMOS technology. CPBL based counter reduces at most 60% energy compared with CPAL counterpart operating from 25MHz to 200MHz and 68% compared with static CMOS from 50MHz to 500MHz.