並列トランジスタに基づいたエネルギー回収回路のデザイン

抄録

This paper presents a new circuit for energy recovery.It can work at more high frequency than 2PDADCL（2-phase Drive Adiabatic Dynamic CMOS Logic）.The proposed structure can work at more than 200M Hz.And this structure also reduces the switching activity than the dynamic logic.This paper also presents a structure of clock generator,which works with the proposed circuits to make up the energy recovery circuit.We have designed an adder using the proposed structure.These logic gates and circuits have been simulated in CADENCE design tool at 180nm technology.The simulation results are also in this paper.