高速応答回路によるLDOレギュレータ特性

抄録

An output capacitor-less low dropout regulator with three quick-responding (QR) loops is implemented in 0.18 um CMOS technology. The proposed capacitor-less LDO has high stability for a current load from 0 to 100 mA and a capacitor load of 100 pF while the dropout voltage is 200 mV. The line regulation is 0.95 mV/V and the load regulation is 20 uV/mA. The quick-responding loops can effectively reduce the overshoot and undershoot. When the load current switch between 0 and 100 mA with 1 us edge time, the maximum overshoot and undershoot are 36.13 mV and 36.81 mV under a 1.2 V supply voltage. And setting time is about 1.8 us.