レイアウト情報に基づくソフトエラーシミュレータに関する研究

抄録

Due to reaching the nanoscale transistor size, effect of single event upset (SEU) to the memory has become conspicuous. In small device geometries, a single particle strike might affect multiple adjacent cells in a memory array resulting in a multiple bit upset (MBU). Traditional fault tolerance technologies such as triple modular redundancy (TMR) and error correcting code (ECC) occupy the large area and have vulnerability to MBU. In this research, we propose soft error simulator developed to calculate bit interleaving distance. Simulation results show that the interleaving distance which can conceal all MBU patterns is 4.