スイッチ向け再構成可能アーキテクチャのためのハードマクロ設計の一検討

抄録

To connect functional chips of a chiplet system with high-performance and high-flexibility, we propose an area-efficient reconfigurable switch whose internal connection topology can be dynamically changed for different applications. In this paper, we implement the essential modules of a switch design, the Arbiter and the Distributor, as hard function blocks for the novel switch-specific reconfigurable architecture. The evaluation results show that the area and delay efficiency can be significantly improved by using the proposed hard function blocks rather than implementing them as soft logics using lookup tables.