抄録
A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P+ poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.
