Logic locking is an efficient circuit encryption method aimed at protecting the intellectual properties (IPs) of hardware designs. It can provide protection against various hardware security threats throughout the IC manufacturing supply chain. Recently, a timing-based logic locking approach known as Data Flow Obfuscation (DFO) has been proposed. DFO creates key-based data flow within the locked circuit, offering resistance against combinational SAT attacks, sequential SAT attacks, CycSAT, and Removal Attacks concurrently. In this paper, we present an approach to unlocking Data flow Obfuscation that is based on structure analysis and SAT solver. Specifically, we first identify the characteristics of obfuscated circuits on signal transition graph and asynchronous pipeline, then conduct structural analysis to prune the key, apply SAT attacks to divide the circuit into real paths and false paths, and finally recover the key. We evaluate on ISCAS’89/ITC’99 locked benchmarks and are able to recover keys in all cases.

An electron injection enhanced bi-mode MOS controlled thyristor (IE-Bi-MCT) structure is proposed by introducing a n-type carrier storage (CS) layer under the p⁺⁺ diverter region of BRT to prevent the extraction of holes during conduction, which leads to the electron injection enhancement (IE) effect similar to IGBT. This is beneficial to the holes accumulated at n CS layer being swept into the p-base region, and the voltage drop across the lateral resistance of the p-base region is increased, which causes the thyristor to be quickly latched up, thus IE-Bi-MCT is converted from IGBT mode to thyristor mode. As a results, the snapback phenomenon is suppressed during forward conduction and conduction loss is significantly reduced. The simulation results show that the snapback phenomenon can be eliminated under the proper parameters of n CS layer, and the on-state voltage drop decreased by about 38% compared with the conventional BRT under 30A/cm² current density.

In this paper, a multi-objective optimization strategy is proposed for the design of high-density low-noise motors. The approach considers efficiency and computational accuracy and uses a wide-frequency-domain multi-operating-condition electromagnetic vibration source as the objective function. The first step is to identify the wide-speed multi-operating-condition vibration source of the motor using the unit-force-wave response method. Then, a multi-objective optimization model of high-density low-noise motors is established by combining electromagnetic design objectives to create a mapping relationship between the electromagnetic noise source and the structural parameters. This method optimizes a 48-slot 8-pole IPMSM for suppression in electric vehicles. The amplitude of the vibration source of the prototype is reduced by 80.73% and 85.48%, respectively, while the average torque remains unchanged. The vibration acceleration of the motor is significantly suppressed under the wide frequency domain multi-operating conditions. This paper provides technical support and design references for engineering applications.

Circuit systems operating in low-voltage applications must provide stable output despite changes in load current. And without IC-level reliability, stable output voltage cannot be guaranteed. In this paper, the LDO regulator is designed to supply and discharge current in a switch format according to changes in load current. Additionally, an ESD protection circuit is absolutely required at the IC level. Therefore, in this paper, area efficiency and high robustness characteristics were verified by developing the ESD protection circuit, rather than using the conventional diode method to prevent ESD phenomenon. As a result, the proposed LDO regulator implemented in the 0.13μm BCD process was confirmed to maintain an undershoot voltage of 87.1mV and an overshoot voltage of 94.1mV at a load current of 350mA.

This paper focuses on the Buck-Boost converter and presents a new approach to improve its efficiency and voltage transformation capability. The approach involves introducing a coupled inductor structure and restructuring the quadric front-end unit to ensure continuous input inductor current. The converter also uses a diode-capacitor (D-C) double-branch structure of switched capacitors to expand the output range and reduce voltage stress on each device. In addition, the converter utilizes the leakage inductance energy to suppress the current surge in the switched capacitor, achieving soft switching. The paper provides a detailed theoretical analysis and compares various indicators horizontally in different converters. Moreover, an experimental prototype of 200W was built to verify the design expectations and theoretical analysis through experiments.

This brief presents a fully integrated automatic impedance-matching RF energy harvesting system that automatically compensates for variations at the antenna-rectifier interface. The control loop is fully integrated on-chip with a low-voltage, low-power design. The design is fabricated in 0.18-μm CMOS technology, and the active chip area is 0.064 mm². The sensitivity optimized by impedance tuning can be improved to more than -30.5 dBm for 0.7 V output at varied initial mismatches, leading to a maximum increase in sensitivity of 5 dB. The control circuit's power consumption is only 2.4 nW, and the minimum supply voltage is 416 mV.

In the research on heat dissipation technology of power chips, the back thinning method is adopted. However, the back thinning technology is facing the risk of causing damage to the chips because the mechanical support capacity of the chip is significantly reduced. To improve the heat dissipation capacity of the back side of the power chips while not affecting the mechanical support, the back side grid type thermal TSV (GT-TTSV) heat dissipation structure is proposed. Based on the proposed heat transfer structure, the heat dissipation structure is optimized and verified, and compared with the heat dissipation structure of back thinning technology. Simulation comparative study shows that the proposed structure has better heat dissipation ability and thermal reliability.

This paper presents a 2: 1 analog multiplexer (AMUX) using IHP’s 130-nm SiGe BiCMOS process. The proposed AMUX expands the analog bandwidth (BW) of CMOS-based DACs by introducing interleaving sampling technique, thus improving the data rate of single lane in modern optical communication systems. Meanwhile, a detailed analysis of process selection which particularly focuses on material and device considerations is adopted, and a principle of the BW expansion is comprehensively discussed. The AMUX exhibits a BW >70 GHz, achieving a data rate of 200 Gb/s under PAM-4 modulation.

Skew angle (SA) is one of the crucial problems in a bit-patterned magnetic recording (BPMR) system. Practically, during the read process, the read head may be tilted up to 30 degrees (°) away from the target track. Without the SA detection and correction mechanism, the performance of the BPMR system will be unbearable. This paper proposes a SA mitigation strategy for a BPMR system based on a multilayer perceptron (MLP) so as to estimate and rectify the SA. Specifically, the MLP-based SA estimator extracts the SA amount directly from the readback signal, which will then be used in the MLP-based detector to produce the estimated recording bits. Simulation results show that the proposed method can estimate the SA embedded in the readback signal more precisely than the conventional one, which just uses a look-up table to detect the SA from the target coefficients. Particularly, for the system operating at an areal density (AD) of 3 terabits per square inch with SA =15° and 30°, the suggested system performs better than the system without the SA mitigation method.

This paper presents an electronic readout system based on the resistance anode, which is capable of processing the output signal from the resistance anode. This design divides the electronic readout circuit into two parts: analog circuit design and digital circuit design. The analog pre-processing circuit the electric charge signal from the resistive anode detector into a voltage signal and amplifies it and the digital part consists of a trapezoidal double-channel shaping algorithm implemented in FPGA. This design overcomes pulse pile-up at high count rates.

Reverse engineering has been a serious threat to integrated circuit hardware security, and gate camouflaging is effective to resist it. Existing camouflage techniques often require process change or rely on emerging devices, and they generally come with significant costs and overhead. In this paper, we propose a novel dynamic camouflage technique based on crosstalk, and used dynamic CMOS to design three camouflaged gates: BUF, AND, and OR. Our technique transmits signal without physical connections, which not only obfuscates the functionality of the logic gates but also conceal the real source of the signal. Moreover, it does not require any process changes. Simulation results show the average area, delay and power overhead is 3.07X, 1.75X and 0.8X respectively comparing to standard dynamic gates. The proposed technique also operates reliably under various Process, Voltage, and Temperature (PVT) conditions.

A monolithic wavelength selective switch (WSS) using a silicon waveguide was fabricated and its characteristics were measured. The crosstalk of the silicon arrayed-waveguide grating (AWG), which is a drawback of the silicon waveguide type WSS, is reduced by introducing a Bragg grating filter (BGF), which can realize a waveguide type WSS with both fast switching and low crosstalk performance. The extinction ratio of the BGF was approximately 20 dB with a 3-dB bandwidth of 0.6 nm. The AWG had an average loss of 9.5 dB with a large second peak crosstalk. Switching experiments showed that the total loss averaged 20.5 dB, the crosstalk averaged -13.9 dB, and that switching responses were 13 μs for both the rise and fall.

The effect of internal radial stress generated during the annealing process on the mobility of through-silicon via (TSV) vertical switch are analyzed in detail, by employing finite element software ANSYS and orthogonal experimental design method. The results show that, the TSV diameter has the largest effect on the mobility of the TSV vertical switch, while the equilateral triangle array produces the smallest effect of stress at the same distance.

This article presents a high-linear phase-locked-loop-based (PLL-based) frequency-modulated continuous-wave (FMCW) frequency synthesizer for 77 GHz automotive radar applications. A behavioral model of the rms FM error by constructing the PLL transient response under a unit frequency step and taking into account the slope of the chirp signal is developed. Simulation results demonstrate the effectiveness of the proposed model in optimizing chirp linearity. The behavioral model is used to facilitate the design of the 77 GHz FMCW synthesizer fabricated in a 55 nm CMOS process. A gain linearized varactor approach is also developed to linearize the voltage-controlled oscillator (VCO) gain (K_VCO) to ensure constant PLL bandwidth maintaining optimum chirp linearity. Measurement results show that the synthesizer achieves a 1.2 GHz chirp bandwidth, a minimum rms FM error of 42 kHz (0.0035% of the chirp bandwidth) under a 4.219 MHz/µs chirp slope while consuming 74.6 mW of power. The measured integer-N mode and fractional-N mode phase noises normalized to 78 GHz are -81.6 dBc/Hz and -80.1 dBc/Hz at 1 MHz offset, respectively.

Thinning of phased only rectangular planar array can reduce the cost and simplify the radio front end of the array. Therefore, it is reasonable to develop the thinning pattern synthesis approach for phased only rectangular planar array. In this letter, a novel computational approach is presented to form the beam pattern and thin the phased only rectangular planar array. First, a new simple matrix equation based on two-dimensional Fourier transform (FT) is derived to calculate the antenna element excitations and the beam pattern. Then, the computational steps to obtain the antenna element excitations with uniform amplitudes are presented. In order to increase the attenuation of the side lobes, the target beam pattern with varied phases determined by a novel analytical formula is proposed. Two examples are used to demonstrate the advantages of the new method. The simulation results show that the new approach can synthesize the beam pattern well, and the new pattern synthesis method has good performance in thinning the phased only rectangular array.

This article presents a second-order cascaded integrator feedforward (CIFF) noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) reusing a dynamic amplifier. The proposed NS architecture uses a gain-optional floating inverter amplifier (FIA) and a sampling-before-integration technique to realize sharp noise transfer function (NTF) with minor extra capacitance. Implemented in 180-nm CMOS technology, the proposed NS-SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 88.6 dB over a sampling frequency of 1.6 MHz and an oversampling rate (OSR) of 16 while consuming only 250 µW. It results in an SNDR-based Schreier figure-of-merit (FoM) of 171.6 dB, proving the proposed ADC fulfils considerable performance with both high resolution and low power consumption.

This work presents a neural network DPD for mmWave RF-PAs. Differently from existing neural network-based DPDs, the neural network in the proposed DPD does not reside in the forward data path. Instead, it estimates the polynomial coefficients from the complex Fourier amplitudes of harmonics during a calibration sweep. It can compensate for PA nonlinearity under various operating conditions with lower hardware complexity compared to conventional DPDs. The proposed design is validated on a 28GHz CMOS phased-array transceiver. In 256-QAM 5G-OFDMA-mode, the proposed neural network DPD achieved an improvement in EVM from -28.7dB to -32.0dB, while maintaining an ACLR of -33.4dBc.

In this study, we proposed a method that could efficiently and comprehensively evaluate power-performance-area (PPA) characteristics of CMOS processes across multiple technology nodes. According to the International Semiconductors Technology Roadmaps (ITRS), we have designed and implemented a series of benchmark Ring Oscillator (RO) circuits using a full-scale downsizing approach from 180nm half-pitch node to 28nm node. Simultaneously, we conducted simulations, analysis, and layout design for RO circuits based on six low-leakage (LL) processes: 180nm, 130nm, 90nm, 65nm, 40nm, and 28nm processes. Through longitudinal analysis and comparison of the PPA characteristics across these six processes, the process quality can be better understood, and some reliable conclusions can be drawn to guide design metrics. The proposed method and benchmark circuits can be well extended to future advanced technology nodes.

A novel capacitor-less low-dropout regulator (CL-LDO) is presented that achieves transient and stability enhancements through the addition of an active capacitor and a dynamically biased buffer. To enhance the transient response, an active capacitor is proposed, resulting in a significant reduction in overshoot, undershoot, and settling time. Furthermore, the dynamically-biased buffer, comprised of a super-gm source follower, effectively enhances the loop stability. Implemented and fabricated in 0.18 μm SOI BCD technology, the CL-LDO generates a stable output voltage of 1.8 V in the input voltage range from 2.8 V to 3.8 V, with a maximum load current of 100 mA and a quiescent current of 94 µA. When the load current steps from 0 mA to 100 mA, the measured results of overshoot and undershoot are 240 mV and 110 mV, respectively. The proposed CL-LDO has superior line regulation of 0.94 mV/V and load regulation of 12.66 mV/A.

To validate the performance of the optical system of the tested equipment, the airborne multi-light source steering device needs to track the mounted equipment on other aircraft during flight tests and provide it with five beacon lights with a maximum span of more than 2 meters and parallelism less than 0.3°. The design, calibration, and flight environment of the airborne multi-light source steering device can affect its pointing accuracy. To address this issue, this paper studies the pointing accuracy of the device, separates its errors, and proposes a method based on the combination of multi-body system theory and finite element simulation. By establishing a mathematical model of pointing errors and relying on finite element simulation to simulate real-world working conditions, the dynamic pointing error patterns are analyzed. Finally, the method is validated through experiments. In the ground dynamic tests, the device's pointing accuracy is 0.2099°, and during the flight tests, the pointing accuracy is 0.231° with an accuracy rate of 90.86%. This proves that the proposed method is highly reliable and accurate.

A cascaded linear active disturbance rejection control multi-stage model predictive control (CasLADRC-MSMPC) method is proposed to provide faster speed and current response, as well as stronger disturbance suppression ability for permanent magnet synchronous motor (PMSM) systems. Firstly, based on the analysis of the discrete mathematical model of PMSM, a multi-stage finite set MPC algorithm is proposed. Secondly, the control performance of the traditional LADRC (TLADRC) algorithm and cascaded LADRC algorithm is analyzed, which provides an excellent controller for the MSMPC algorithm. The MSMPC algorithm is then subjected to the cascaded LADRC algorithm in order to enhance the overall control system’s performance and anti-interference capability. Finally, experimental analysis is conducted on the TLADRC-MPC strategy, CasLADRC-MPC strategy, and CasLADRC-MSMPC strategy. The experimental results show that the proposed algorithm has better current tracking ability and stronger anti-interference ability.

This work presents a novel digital intermediate frequency (IF) module designed for hyperspectral microwave radiometers, enabling the detection of non-uniform channels. The IF module is based on polyphase filter bank and fast Fourier transform techniques, capable of processing sampling data from high-speed analog-to-digital converters (ADC) in real time. The module is implemented on a circuit board featuring a 6.4 gigabit samples per second sampling-rate ADC and Xilinx Vertex-7 field programmable gate array, followed by performance testing and analysis. When combined with an appropriate radio frequency front-end, this IF module can form a hyperspectral microwave radiometer with non-uniform channel detection capability, finding applications in various microwave remote sensing fields.

This paper presents a new method to overcome the degraded control performance of linear induction motors (LIM) due to end effects. The method employs a parameter-self-tuning adaptive sliding mode observer (ASMO) and model predictive current control (MPCC), which first develops a LIM mathematical model considering end effects and then designs the MPCC to strengthen the control. To improve the accuracy of the flux observation, the method develops the ASMO and analyzes the stability of the observer. For parameter tuning, the method utilizes an improved particle swarm optimization algorithm (IPSO). Overall, the experimental findings validate the effectiveness of the proposed algorithm.

In this work, the design of a 0.18μm CMOS dual loop capacitor-less low-dropout regulator (LDO) to achieve fast-transient response and good power supple rejection (PSR) is proposed for system-on-chip (SoC) power supply. The proposed LDO has a high slew-rate fast loop for enhancing transient response capability, and the high gain slow loop to improve PSR. Results show that the LDO consumes 100μA quiescent current, delivering a 50mA load current over a 30pF load. The maximum transient output-voltage variation is within 10% of the output voltage with recovery time of less than 81ns with a load step between 500μA and 50mA with 50ns edge times. The PSR is better than 50dB at 1MHz.

Defect pattern detection of wafer bin maps (WBMs) is vital in wafer quality improvement owing to preventing further defects and resource waste. We proposed two Mixup approaches to train Vision Transformer under only single defect WBM samples for mixed-type defects recognition. We use UnionMixup and Token level Max-Min-Saliency Mixup to generate mixed-type defect WBMs to feed Vision Transformers. In the recognition of two-mixed defect types WBMs, our method improves 17.1 % compared to baseline (none mixup) and we have 1.7% accuracy gain compared with state-of-the-art mixup approaches. In the recognition mixed defect samples containing more than two-mixed defects (three-mixed and four-mixed), we gain at least 24.7% (compared with baseline) and 11.1% (compared with single SOTA mixup) respectively. The combination of Union Mixup and Token level Max-Min-Saliency Mixup become better than other SOTA mixup methods obviously in mixed patterns including more than three defects.

We have introduced a sub-nanometer non-contact displacement sensing method using phase-diversity optical digital coherent detection. The initial work achieved 0.62 nm displacement sensing with a 0.21 nm resolution using a temporal domain filter. However, optimizing the filter for a sharp transition band and low order posed challenges, limiting noise filtering. To overcome this, frequency-domain filter is proposed and investigated in this work. Employing a frequency-domain bandpass filter improved resolution to 0.07 nm at 0.62 nm displacement, resulting in an 18.5 dB signal-to-noise ratio—8 dB higher than temporal domain filtering. This advancement enhances precision for applications in precision instruments without any additional cost.

Hybrid switch (HyS) consisting of Si IGBT and SiC MOSFET becomes increasingly popular due to its prominent advantages of low power loss and cost in clear energy era. However, the existing studies suffer from the current measurement methods due to the insertion inductance and inductive signal overshoot, which may lead to inaccurate measurements of loss, electrical stress and also limited performance of HyS at high switching frequencies. This paper conducts an in-depth study on the impact of inner loop inductance on HyS turn-off process. And an accurate current measurement method is proposed for high frequency HyS test and application, showing significant improvement in insertion inductance level and high-bandwidth accuracy.

This paper proposes a wide-band and wide-angle scanning Ku/Ka dual-band phased-array antenna. The dual-band antenna array consists of Ka-band PCB-based slot antenna elements and Ku-band metallic banyan tree antenna elements. The operating bandwidth of both bands is extended to 4GHz, and the beam scanning coverage achieves ±60° and ±30° for Ku and Ka bands, respectively. By special treatment of the PCB, the channel isolation between Ku and Ka elements is better than -30dB and -18dB in two bands, which can support the simultaneous working situation of both antennas. Besides, the feeding structures of both antennas are flexible to be utilized in a phased-array system. A prototype of Ku/Ka antenna array is also fabricated. The measured active VSWR, channel isolation and scanning patterns are in good agreement with the simulated results, which demonstrates its good radiating performance and indicates the promising application in advanced phased array systems.

This letter presents a broadband, high-precision bidirectional passive 6-bit digital phase shifter (DPS) designed for phased array systems. We propose three novel structures: the dual modified magnetically coupled all pass network (DMMCAPN) for small phase shifts, the modified high pass network/modified magnetically coupled all pass network (MHPN/MMCAPN) for medium phase shifts, and the Lange/modified transmission line network (L/MTLN) for large phase shifts. It shows a phase shift range of 360° with a step of 5.625°. Measurements in the 6.5 - 13.5 GHz range indicate that the root-mean-square (RMS) phase and amplitude errors for the 64 states are within 1.8 ° and 0.75 dB, respectively. Additionally, the average insertion loss is (-12.2 ± 0.5) dB and the input 1 dB compression point (IP1dB) is 29 dBm at IF 10 GHz. To the best of our knowledge, this letter presents an exceptionally high degree of phase shift accuracy across the broad bandwidth, outperforming other GaAs passive digital phase shifters. Furthermore, it showcases superior linearity when compared to silicon-based passive digital phase shifters.

An application dependent FPGA interconnect testing scheme is presented. The goal is to reduce the number of test configurations while keeping high fault coverage. Reduction is done by using SMT constraints that allow multiple nets as a group to use one input vector, so that the number of test configurations is reduced. Based on the complete fault model, a novel approach to generate SAT formulas, most notably dominant bridging faults, are explained to retain coverage. Experiments on FPGAs shown that this method yield on average 44% fewer configurations on circuits with 1000∼100000 LUTs comparing with existing methods, with full fault coverage.

To make the motor perform better during operation, a conical outer rotor structure is proposed based on the traditional outer rotor permanent magnet vernier motor (PMVM) structure. The electromagnetic characteristics of PMVM and COR-PMVM are compared and analyzed. The parameters of COR-PMVM are optimized, and the motor's temperature rise is simulated and analyzed by magneto-thermal coupling. Simulation results demonstrate a 39.3% increase in electromagnetic torque of the engine, and a 33.3% reduction in torque ripple. The stator and winding can reach a temperature of 101.72 °C, whereas the rotor and permanent magnet remain cooler at 70 °C. Lastly, a temperature rise experiment is conducted on the permanent magnet motor to validate the precision of the magneto-thermal coupling analysis method.

This paper presents a low dropout regulator (LDO) with a low quiescent current which helps to extend the standby time of battery-powered electronic devices. By utilizing the switchable bias technique in the error amplifier (EA), the bias current is switched to a higher level to accelerate the transient response under heavy load, while a low bias current is applied to EA to maintain a low quiescent current under light load. High speed current comparators and hysteresis control are combined to ensure fast and stable switching operation of the bias current. Moreover, an inrush current suppression circuit is proposed by recycling the switchable bias in EA. During startup, the bias current of EA can be kept low, and a reduced slew rate can be obtained at the pass gate voltage. The proposed LDO has been fabricated in 0.18-μm CMOS process, The experimental total quiescent current is 300nA under no-load condition. The maximum load current is 300mA. Measurement results show that the LDO can be settled within 8μs for a load current step of 0-50mA. In the startup process, the measured inrush current can be effectively limited.

Nanopore-based DNA sequencing technology features the advantages of label-free, low-cost, and rapid detection. However, the existing nanopore sequencing readout cell or array for the lower area and power consumption become prohibitive. This brief presents a low noise potentiostat readout array. Based on the five-transistor OPA, the half-shared amplifier reduces the area and power consumption of the cell by about 50%, and shows a good suppression effect on mid-to-high frequency noise in the output channel. As a result, high-throughput is achieved with low noise. The performance of the proposed array channel has been evaluated in 180-nm CMOS process, the input-referred current transient noise was 2.28 pA_RMS, the power consumption was 2.2 µW and the unit area was 10×12 µm².

To improve the tracking processing speed of embedded Global Navigation Satellite System (GNSS) receivers, we propose seven custom instructions and a tracking accelerator integrated into the self-developed 32-bit RISC-V processor named Prism. The accelerator can increase execution speed significantly at a reasonable area and power cost. The FPGA test and synthesis under the 40nm technology showed that the accelerator achieved 58% to 94% speed increase for three tracking loops, and 122% to 700% speed increase for seven custom instructions, at the cost of 33.1% more area and 19.8% more power consumption.

The Wuhan Ionospheric Sounding System (WISS), based on FPGA and DDS architecture with USB communication, was developed for studying the ionosphere by the Ionospheric Laboratory of Wuhan University. This letter presents an improved hardware system of WISS, which is based on network port communication and suitable for software defined radio. The output waveforms are more controllable and more diversified in the improved system than the previous version. The new version of ionospheric sounding system can not only conduct conventional ionospheric exploration, but also implement meteors sounding by VHF band. The system structure and the design scheme of each module are described in detail. Then, some typical experiment results are carried out to verify the performance of the improved system. Results show that the new version system performed well in the experiments of ionospheric meteors sounding.

Due to the low noise and high linearity characteristics of GaAs Hetero-junction Bipolar Transistors (HBTs), Low Noise Amplifiers (LNAs) are widely used in aerospace, communication, computer, and other fields. Extracting device model parameters is of great significance for subsequent research on the electromagnetic compatibility characteristics of such devices. In this paper, based on the small signal model, the model parameters of the amplifier are extracted by combining the I-V characteristics of the amplifier under different external voltage conditions. The linear model parameters are extracted using a fitting analysis method to obtain the Pspice circuit model of the GaAs amplifier under normal operating conditions. The simulation results align closely with the measured results. Compared with traditional modeling methods, this approach effectively resolves the issue of being unable to measure parameters due to chip packaging. This method holds substantial significance in extracting circuit model parameters and conducting in-depth research on circuit electromagnetic compatibility characteristics of this device.

This paper presents a bandgap reference (BGR) circuit with high precision and low power, which is suitable for wide supply and temperature range DC-DC converters. A thermal compensation method is designed to improve output accuracy. A thermal shutdown detection (TSD) circuit is proposed to prevent overheating. It also adopts a two-channel pre-regulator, which reduces the current consumption and area while enhancing PSRR. The measured results show the temperature coefficient (TC) stands at 5.69 ppm/°C in the range of -40°C to 155°C. The typical current consumption is 0.84μA in the supply range from 3.5 to 40 V. The PSRR is -86dB at 1kHz.

A wideband crossed dipole antenna for dual-polarized applications is presented in this paper. The antenna consists of a printed crossed dipole radiator loaded with periodic slots, four metal posts, four metal sidewalls and a metal reflector. The crossed dipole antenna is directly fed by a simple coaxial cable, achieving stable dual-polarization radiation characteristics. Here, two approaches are adopted to adjust the high and low resonant frequency of the antenna with large freedom. Firstly, four metal posts are introduced into conventional crossed dipole antenna, and their distance from the feeding point can independently adjust the lower resonant mode. Secondly, periodic slots are etched on the crossed dipole arms, and the upper resonant frequency can be controlled independently by altering the length of these slots. Also, the metal sidewalls on the ground are used herein to obtain enhanced gain property. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The measured results show good performance of a relative bandwidth of 64.3% for VSWR ≤ 2 (1.32-2.57 GHz). Moreover, the antenna has good unidirectional radiation performance and can achieve maximum gain of 9.1 dBi at 2.3 GHz.

In order to solve the problems of the traditional model reference adaptive system (MRAS) speed estimation adaptive mechanism, such as poor tracking accuracy and slow response, A new dual sliding mode adaptive observer is designed to estimate the rotational speed and rotor position of permanent magnet synchronous motor (PMSM). Firstly, a new two-variable complex reaching law is used to replace the traditional first-order sliding mode for velocity loop control, and an anti-saturation scheme is introduced to improve the anti-interference ability of the system. Secondly, the PI adaptive mechanism in the traditional MRAS is replaced by a new super-twisting weighted integral type algorithm adaptive observer (STWITA-AO), which effectively speeds up the convergence of the estimated speed and reduces the inherent chattering of the sliding mode structure. Finally, the relevant simulation is compared and verified. The simulation results show that the estimation strategy based on the new double sliding mode MRAS control can make the speed estimate converge to the actual value faster, and improve the dynamic performance and robustness of the observer.

The novel rare earth variable flux permanent magnet synchronous motor (PMSM) for electric vehicles is proposed. The structure and magnetic field regulation characteristics are analyzed, the variation of magnetic density, no-load back electromagnetic force and output torque with speed was studied through finite element simulation. The weak magnetic field expansion speed performance of the novel PMSM has been verified through experimental equipment. The adjustable electromagnetic field with running speed on the rare earth PMSM increases the high-speed operation range of vehicle.

A wideband dual-line polarized antenna with low-profile property is presented in this paper. The dual-polarized antenna consists of two crossed antenna elements over a metal reflector and is excited by RF connectors vertically. Here, the crossed antenna element is based on Vivaldi radiator to obtain wideband performance. By loading resistors on the patches of Vivaldi radiator, not only the impedance matching of the proposed antenna can be improved further but also the profile is reduced greatly. Whatever, the loaded resistors can also depress radiation efficiency of the antenna element to a certain extent, especially in the lower band. For this reason, three periodic slots etched on the Vivaldi radiator are introduced herein to enhance the gain performance. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The results show good performance of a relative bandwidth of 153% for VSWR ≤ 2 (2-15 GHz) and a low profile of 0.22 λ_L (in terms of the lowest frequency of the band). Besides, the prototype can achieve an average gain of approximately 5 dBi and a maximum radiation efficiency of 80% within passband.

Level-increased nearest level modulation (NLM) has been widely used in the modular multilevel converter (MMC) due to its simple implementation and low switching frequency in recent years. However, there are some disadvantages such as the poor performance of output voltage distortion and harmonic circulating current. A harmonic circulating current (CC) suppression method based on level-increased NLM is proposed in this paper. The impact of level-increased NLM on the CC is firstly analyzed. Then, a 5-voltage-level compensation method for harmonic CC suppression is proposed. Simulation and experiment verify the effectiveness of the proposed method.

A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency ( f_T). Broadband operation is achieved using an enhanced degenerated Darlington f_T-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional f_T-doubler structures, the enhanced cascode Darlington f_T-doubler structure reduces the “V_CE mismatch” between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher V_CE for amplifying transistors, which represents higher f_T,_peak performance. Benefiting from the proposed Darlington f_T-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181- f_T bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

To improve the dynamic response performance and robustness of a permanent magnet linear synchronous motor (PMLSM)-based servo system, an adaptive proportional-integral-derivative (PID) controller based on a particle swarm optimization neural network is proposed. First, according to the mechanical dynamics equation of the PMLSM, a mathematical model of the PMLSM was established. Second, an adaptive PID speed controller is designed to realize real-time control of the PMLSM. To improve the dynamic performance and stability of the controller, a particle swarm optimization neural network is used to dynamically tune the parameters. Finally, the effectiveness of the proposed controller was verified on the MATLAB/Simulink simulation platform. Compared to the traditional PID controller, the adaptive PID controller can improve the dynamic performance of the system more effectively.

A novel buck-boost power converter is proposed to improve the performance of switched reluctance generator (SRG) system in an electric vehicle. In the proposed topology, the energy conversion part is formed by a buck-boost circuit and additional switches, with which, it is flexible to significantly boost the magnetization voltage and demagnetization voltage, thereby the output power range is improved and the power losses are reduced. The basic structure of the proposed converter is presented first and the attached operating modes are analyzed. The control strategy of the SRG system is then made to control the output voltage and the boost capacitor voltage. The simulation results show that compared to the conventional buck-boost converter, the proposed converter enhances the efficiency and reduces the power losses.

How to replace the referee in sports with artificial intelligence has attacked a huge amount of attention recently. In this paper, non-battery pressure detection and communication system are designed and fabricated aiming to help the referee in the basketball games. To get the information from player and ball at the same time, the designed system is consisted of three parts, including the basketball monitoring system, the shoes monitoring system, and the laptop to collect and process the data. For the basketball monitoring system, eight piezoelectric polyvinylidene fluoride (PVDF) flexible thin films are used as the sensor on the surface of the basketball with the sensitivity of 0.065 V/N and four hard piezoelectric Lead Zirconium titanite (PZT) patches are set inside the ball as the power source. As for the shoes monitoring system, four PZT patches work as both power source and pressure sensor with a sensitivity of 0.025 V/N. To solve the referee problem in basketball game, time delay of different systems is first measured. The different systems have similar time delay of about 3s, which will help to make sure whether the players break the rules. In this paper, whether the player has a traveling violation in a game can be refereed by the collected data, which has more than 97% accuracy. This work shows an innovative progress in automatic referees in games and the Internet of Things (IoT) in the human health monitoring.

Approximate computing has excellent result in error-tolerant applications sacrificing computational accuracy for better performance in the area, speed, and power consumption. As the most basic operation, addition is used in a large number of applications in various occasions. Therefore it is of great importance to optimize the performance of addition computation. In this paper, a segemented carry prediction adder (SCPA) structure is proposed, which splits the long carry chain into several short chains for parallel computation. The design parameters are diversified by adjusting the size of the blocks and the prediction depth of each subadditive to achieve different levels of performance. Flexible parameter tuning allows different design goals to be achieved based on specific performance requirements, which makes SCPA a useful design guideline for approximate adders. The error performance of SCPA is mesured by MRED, NMRED, ER, and other indicators and significantly has the best statiscal performace compared to similar designs. The proposed design is synthesized under TSMC 65nm process, and the result shows that the SCPA has a very nice accuracy-power tradeoff under 8-bit and 16-bit condition.

Transient execution attack does not affect the state of processor microarchitecture, which breaks the traditional definition of correct execution. It not only brings great challenges to the industrial product security, but also opens up a new research direction for the academic community. This paper proposes a defense mechanism for SMT processors against launching transient execution attacks using shared cache. The main structure includes two parts, a security shadow label and a transient execution cache. In the face of the side channel attacks widely used by transient execution attack, our defense mechanism adds a security shadow label to the memory request from the thread with high security requirement, so that the shared cache can distinguish the cache requests from different security level threads. At the same time, based on the record of security shadow label, the transient execution cache is used to preserve the historical data, so as to realize the repair of the cache state and prevent the modification of the cache state by misspeculated path from being exploited by attackers. Finally, the cache state is successfully guaranteed to be invisible to any attacker’s cache operations. This design only needs one operation similar to the normal memory access, thus reducing the memory access pressure. Compared with the existing defense schemes, our scheme can effectively prevent Spectre attack, and the overhead of performance is only 3.9%.