This paper proposes a Reverse Conducting Base Resistance-controlled Thyristor with P-body region(P-RC-BRT), which has high dV/dt immunity and achieves blocking at zero gate voltage. The characteristics of P-RC-BRT were compared with the conventional BRT and RC-BRT, and the pulse discharge characteristics of devices with different circuit parameters were analyzed, which were as high as 6208 A and 130.8 kA/μs. The dV/dt immunity of the devices was studied comparatively, the P-RC-BRT has higher dV/dt immunity.

Cascaded active EMI filters offer superior suppression performance compared to single-stage filters, but the required number of components increases proportionally with the number of stages, resulting in larger volume and higher cost. To address this issue, this paper proposes a multi-channel active common-mode EMI filter based on magnetic core and chip reuse. In the proposed structure, multiple cascaded filter modules share a single current-sensing magnetic core, effectively reducing the number of magnetic components and lowering both hardware cost and structural complexity. Additionally, by employing a dual-channel high-speed operational amplifier (AD826), the design enables chip-level reuse in the signal amplification stage, further improving integration and compactness. A dual-feedback cascaded architecture is adopted to enhance common-mode EMI suppression without significantly increasing hardware resources. Experimental results based on a boost converter platform validate the effectiveness of the proposed filter in achieving both high suppression performance and efficient component utilization, making it well suited for power electronic systems operating in complex electromagnetic environments.

Fault-tolerant and redundant power supplies are often used in systems that require high reliability, such as data servers, telecommunications, and power supplies for autonomous driving function. Using diode is a simple method to keep uninterrupted power supply that is, using diode in series with each power path to become “Diode ORing”. However, in high current application, the voltage drop of the diode will result huge power loss. Even if that a low voltage drop of Schottky diode is adopted. This article proposes a simple P MOSFET control circuit that can implement the function of P MOSFET as a diode, that is, to ensure unidirectional conduction of current and maintain a low conduction voltage drop, thereby reducing losses. The circuit has the advantages of low forward voltage drop, without IC control, no need for additional auxiliary power supply, and the ability to block current flow between different power supplies that is the reverse current blocking is achieved. A circuit for implementing ORing of two power supplies to increase system redundancy or power capacity is provided. Simulation results verify the feasibility of the proposed control circuit.

Binary matrix-vector multiplication (BMVM) is a key operation in post-quantum cryptography schemes like the Classic McEliece cryptosystem. Conventional computing architectures incur significant energy efficiency loss due to data movement of large matrices when handling such tasks. Resistive memory (RRAM) non-volatile compute-in-memory (nvCIM) is an ideal technology for high energy-efficient BMVM processing but faces challenges, including signal margin degradation in high input-parallelism arrays due to device non-idealities and high hardware overhead from current readout and XOR operations. This work presents a RRAM nvCIM architecture featuring: 1) 1T1R cells with high-resistive-state compensation modules; and 2) pulsed current-sensing parity checkers. Based on the 180nm process and test results from RRAM devices, the computing accuracy and efficiency of the architecture are verified by simulation. The proposed architecture performs high-precision current accumulation with a maximum MAC value of 10 and achieves an energy efficiency of 1.51TOPS/W, offering approximately 1.62× improvement compared to an advanced 28nm FPGA platform.

Modern solid state drives (SSDs) based on NAND Flash Memory (NFM) have multi-level parallel resources to enhance their I/O performance. The page allocation policy, which is responsible for allocating logical pages to physical parallel resources, directly affects the efficiency of SSD parallelism utilization. Traditionally, the load-balancing page allocation policy relies on the number of commands rather than their actual latency. However, this policy fails to effectively balance the execution latency skew among the various parallel units of SSD, leading to parallelism loss.

To address these problems, we propose a load-balancing method based on latency estimation called LEPA. Instead of relying on the number of commands, LEPA estimates the waiting latency of commands in pending to determine the load. Our experimental results indicate that our latency estimation-based load balancing page allocation significantly reduces the die load skew (by 85.9% on average) caused by the inaccurate estimations of traditional methods, with minimal overhead. Moreover, LEPA demonstrates an 8.0% improvement in plane-level parallelism. As a result, the proposed method effectively improves SSD system I/O performance and reduces request response time by 14.7%.

In this paper, an AC-DC constant current buck converter is designed, and a novel high voltage self-powered method of chip is proposed. Through the VIN valley power supply technology, the serious problem of heating for integrated high voltage power supply of AC-DC converter is solved, and making high voltage integrated power supply of high power system possible. The chip is designed and produced in 0.18μm UHVBCD process. A 50W BUCK converter prototype with this chip as the core is developed. The test results show that the constant current performance is good, with the line regulation is 1.7%, and the load regulation is 3.2%. The chip temperature is lower than 110°C. The experimental results of prototype demonstrate the effectiveness of the proposed circuit. This design reduces peripheral devices, saves costs and improves the integration degree.

In this paper, appearance, defects and electrical properties of 29-year-old PV modules in operation was studied. Almost all PV modules are visually intact, the appearance detects were mainly the peeling, blackening of the tin-coating strip and aging of aluminum alloy frames.The open circuit voltage (Voc) decreased slightly with annual degradation rate of 0.048%. The annual degradation rates of the short circuit (Isc), maximum power point voltage(Vmp), maximum power point circuit(Imp) were 0.38%, 0.91% and 0.93%, respectively. The power decreased significantly with annual degradation rate of 1.59%.The attenuation trend of power and (fill factor) FF is completely consistent.

This paper presents a 900-MHz low-power low-IF receiver for narrowband Ambient Internet of Things (A-IoT). To reduce the power consumption of the clock generation module, a free-running ring oscillator (RO) is employed. To mitigate the impact of RO initial frequency drift on sensitivity, a preamble-based frequency estimation (PBFE) algorithm is proposed. To suppress image interference, a passive mixer based on a Gm-C cell is implemented on-chip. Designed in 55-nm CMOS process, post-layout simulation results show that the proposed receiver achieves a link gain of 80-dB and a noise figure of 9.8-dB at 1-MHz IF. For a 90-kbps on-off keying (OOK) signal, the receiver demonstrates a sensitivity of -93-dBm and an image rejection ratio of 7.5-dB. The prototype operates at 1.2-V supply and consumes a total power of 580-μW. The model verification based on chip simulation results verifies that the PBFE algorithm improves sensitivity by 6-dB.

A terahertz-wave subharmonic mixer receiving RF input and local oscillator (LO) signals from the opposite side of a planar antenna was developed based on epi-layer-transferred Fermi-level managed barrier diodes on a SiC substrate. The developed mixer mounted on a Si hyperhemispherical lens with a transimpedance amplifier exhibited a minimum noise-equivalent power as low as 6×10^-19 W/Hz at RF and LO frequencies of 306 and 151 GHz, respectively. Comparison of signal-introduction configurations revealed that a single planar antenna simultaneously acted as an antenna for RF and LO signals as well as a signal combiner for mixing detection.

Spiking neural networks (SNNs) often face security and resource constraints, highlighting the need for lightweight hardware solutions. Tunneling field-effect transistors (TFETs) offer low-power operation for leaky integrate-and-fire (LIF) neurons due to their unique current mechanism. This work proposes a physical unclonable function (PUF) architecture based on TFET-LIF neurons for secure edge SNN applications. Leveraging random dopant fluctuation (RDF)-induced randomness in germanium-channel DG-TFETs as an entropy source, we emulate LIF behavior and analyze the impact of RDF, and work function variation (WFV). RDF is identified as the dominant factor influencing firing threshold (V_TH-LIF). A compact circuit is used to extract PUF responses, and every spike consumes 0.27 fJ. The PUF shows high reliability (≥97.11%), 49.8% uniqueness, and passes the NIST randomness test, enabling secure key generation and authentication.

A cross-symmetric main&tail inductor with high area utilization is proposed originally. The proposed cross-symmetric main&tail inductor improves the area utilization by using the redundant area of the octagonal main inductor while optimizing the LC-VCO phase noise. Compared with the conventional inductor, the unit area utilization rate is increased from 82.84% to 87.13%. Phase noise is achieved as -129.5 dBc/Hz over LC-VCO based on the cross-symmetric main&tail inductor, which is lower than -120.4 dBc/Hz of the conventional inductor. The output frequency range of the LC-VCO is 2.295 GHz ∼ 3.080 GHz, and FOM of LC-VCO is 193.8 dBc/Hz.

The single-transistor-clocked DET (STC-DET) effectively addresses the timing convergence issue in single-edge-triggered for high-frequency applications while reducing power consumption losses caused by redundant transitions. However, the introduction of the single-transistor-clocked buffer creates a more complex transistor stress distribution as well as a transmission network, and the low-power strategy based on a low supply voltage also makes the circuit more sensitive to threshold voltage degradation. This paper focuses on the STC-DET flip-flop as the research subject, employing transistor-level aging analysis to identify aging-sensitive transistors through de-aging analysis. A combination of transistor-level gate length tuning strategy and circuit structure optimization is applied for effective anti-aging design. Analysis results show that this optimization strategy significantly reduces the overall delay increase after aging under all corners. Notably, under the typical TT process corner, the 0→1 delay increase of the BOTTOM module is reduced by 58.2%, demonstrating the superiority of the proposed method.

A compact tri-band bandpass filter based on spoof surface plasmon polaritons (SSPPs) is proposed. The design utilizes an SSPP unit cell that combines short-circuited and open-circuited stubs to support the fundamental mode and two high-order modes, enabling tri-band filtering. Independent bandwidth design is realized during the design stage by precisely adjusting specific geometric parameters. A prototype was fabricated and measured, with results showing excellent agreement with simulations, confirming the accuracy and effectiveness of the design. The filter exhibits low insertion loss, independently designed bandwidths, and a compact size, making it suitable for modern multi-band wireless communication systems.

In this letter, a novel load design space is proposed based on the resistance-resistance series of continuous modes (Res.-Res. SCMs) for designing high-efficiency power amplifiers (PAs) with multi-octave. By introducing a phase shift parameter into the voltage waveform expression of Res.-Res. SCMs, the load design space is expanded, enabling greater design flexibility and bandwidth enhancement. To validate the proposed approach, a multi-octave PA was designed and implemented using a GaN HEMT. Measurement results show that the PA achieves a drain efficiency (DE) of 55.3%–73.9%, an output power of 38.7–41.2 dBm, and a gain of 9.7–12.2 dB across 0.5–3.9 GHz, corresponding to a relative bandwidth of 154.5%.

This paper proposes a wide-range, energy-efficient differential cascade voltage switch (DCVS) Level-Shifter (LS), incorporating a cross-coupled pull-down auxiliary network to balance contention. It aims to provide a solution of contention problem in DCVS and improve its limited voltage conversion range. By comprehensively utilizing current-limiter, split-inverter, and multi-threshold transistor technology, the voltage conversion range is further expanded, and power consumption is reduced. In this design, the NMOS network is configured as a super-cut-off state during static conditions, significantly decreasing leakage power. The design is implemented based on 55nm process. Post-simulation indicates that at a frequency of 1MHz, the transmission energy is only 19.97fJ (0.3V-1.2V), minimum voltage is 0.15V. The leakage power is extremely low, at only 117.4pW (0.3V-1.2V). Five LSs designed with similar processes were also re-implemented with 55nm technology, and post-simulation shows that our design exhibits the lowest leakage power and transmission energy. Comprehensive comparison with others also proves that proposed design has reached the advanced level.

With the rapid development of 5G technology, key components like Surface Acoustic Wave Filters (SAWF) face challenges in bandwidth, spurious, and leakage. This paper optimizes the materials, thickness, and metallization ratio (MR) of IDT to propose a high-frequency, low-spurious, wide-bandwidth filter for the N78 band. Firstly, simulations show Au outperforms Al and Cu in reducing spurious and leakage. Secondly, by analyzing impact of MR, the optimal MR for series and parallel resonant units is 0.4 and 0.6, respectively. Eventually, A filter with 642 MHz bandwidth, 3.52 GHz center frequency, and 1.22 dB in-band spurious was obtained for N78 band.

This study proposes an automated fault diagnosis method for switch faults in three-phase inverters, based on current waveform feature extraction. The research focuses on analyzing three-phase output current waveforms under different fault conditions, including open-circuit fault (OCF), short-circuit fault (SCF), gate driver fault (GDF), and aging (AGN). Multiple key indicators such as average current, root mean square (RMS) current, peak-to-peak value, and Park’s current are extracted, and two normalized current indices are proposed as the basis for fault identification. The proposed approach can be seamlessly integrated into existing current sensors and control algorithms, requiring only minimal software adjustments. Moreover, the method is robust and applicable under varying conditions consistently achieving high diagnostic accuracy.

In this letter, a wideband 180° hybrid coupler with unequal power division ratio and inputs absorptive behaviors is proposed, which consists of a slotline-based four-port network (FPN) and two absorptive cells. The slotline-based FPN is implemented by four transmission line sections, a slotline resonator, two microstrip/slotline transitions and a shunted open-circuit stub, which can achieve wideband isolation and unequal power division. Both absorptive cells are composed of a coupled line and a resistor-loaded shorted stub, which can not only enhance the bandwidth of the hybrid coupler, but also achieve inputs absorptive behaviors for both Port 1 and Port 4. Explicit design equations and detailed analysis are given and discussed. Meanwhile, a prototype with unequal power division ratio of 1:2 and absorptive bandwidth of 200% is selected for design, fabrication and measurement. Finally, the excellent agreement between the EM simulated results and the measured results verifies the effectiveness of the design.

This paper presents an adjustable CMOS voltage reference that achieves a low temperature coefficient (TC) through a novel curvature-compensation technique. The design employs thin/thick-gate NMOS and PMOS pairs to generate complementary voltages (ΔV_GS and ΔV_SG) with opposing second-order curvature. Dynamically scaling ΔV_GS via a programmable k-coefficient and summing with ΔV_SG enables output adjustability and low TC. Implemented in 180 nm CMOS, post-layout simulations show 0.5-0.95 V output range with average TC of 5 ppm/°C (best) to 15 ppm/°C (worst) from -40°C to 125°C. The circuit consumes 456.5 nA at 27°C and achieves -51 dB PSRR (@100 Hz).

In this paper, we proposed two kinds of novel XOR gate circuits by using two memristors and four CMOS transistors. The architecture with two positive terminal of memristor connecting realizes AND and XOR logic simultaneously, while the other architecture with the negative terminal of memristor connecting achieves OR and XOR logic simultaneously. Furthermore, these two kinds of hybrid memristor-CMOS XOR logics are further used to build two kinds of single-bit full adders, and the adder circuits are verified by SPICE simulation. Our proposed full adder circuits have a smaller area and lower energy consumption compared to the CMOS technology.

This paper presents a Robust Adaptive Extended Kalman Filter (RAEKF) method to improve the disturbance rejection control of permanent magnet synchronous motors (PMSMs). PMSM equations are first established. Next, an improved extended Kalman filter is employed to estimate the states of the PMSM, accompanied by adaptive adjustment of the measurement noise covariance matrix. Finally, apply the optimized exponential reaching law in the sliding mode speed controller to improve the response speed. The efficacy of the proposed method is validated through experiments conducted on a 100W PMSM.

There is a contradiction between the number of communication channels and the number of sensors for wearable sensing systems. Increasing the number of sensors improves monitoring accuracy and function but makes communication difficult because of the increased channel necessity. In this paper, we developed a multi-sensor wearable system with only one single transmission channel and applied it to running gesture monitoring. By combining the k-nearest neighbor (kNN) machine learning method for signal analysis, we achieved classification of different running gestures. The implementation of a single signal transmission channel is based on hardware-level amplitude modulation, which is realized by designing the flexible piezoelectric Polyvinylidene fluoride (PVDF) sensors into various sizes. The different sizes enable amplitude modulation of the sensed signals. The modulated signals from different sensors are merged into a single-channel signal and transmitted to a personal computer via a wireless transmission circuit powered by a piezoelectric energy source inside the system. By utilizing the kNN algorithm, we successfully classified signals with different characteristics. Ultimately, two distinct running gestures were successfully detected and differentiated. This design presents an effective method to reduce signal transmission pathways and energy consumption, while also demonstrating that artificial intelligence algorithms can efficiently analyze data to extract useful information. This design method may provide broad inspiration for the development of wearable devices and holds significant promise for sport sensing.

The peak-to-peak current in dual-active-bridge (DAB) converters significantly impacts conversion efficiency. Under conventional single-phase-shift (SPS) modulation, efficiency degrades at high voltage conversion ratios. This paper proposes an asymmetric duty cycle-based triple-parameter modulation (TPADM) strategy by introducing asymmetric phase-shift angles to expand modulation flexibility. First, the operating principle of TPADM is analyzed, identifying four distinct modes based on switching sequences. Second, steady-state characteristics (inductor current, power transfer) are derived via time-domain analysis for all modes. Third, a piecewise optimization method using Karush-Kuhn-Tucker (KKT) conditions minimizes peak-to-peak current, maximizing efficiency. Finally, experimental results validate the superiority of TPADM over SPS in reducing current stress and improving efficiency across wide voltage ranges.

This paper proposes a fault detection algorithm addressing both common open-circuit faults and unique continuous current faults in three-phase full-bridge switches for SRM with ring winding structure. By employing a decoupling computation of three-phase winding currents, fault signatures independent of operational state variations are derived. Following fault detection, adaptive thresholds dynamically adjusted with motor operating conditions are implemented for current analysis, enabling precise identification of fault types and locations through advanced signal processing. The developed methodology achieves online automatic diagnosis of conventional open-circuit failures and SRM-specific continuous faults in the power conversion system. Experimental validation under varying speed and load conditions demonstrates the algorithm's rapid response, diagnostic accuracy, and robust performance consistency, confirming its effectiveness for real-time fault monitoring in SRM drive applications.

Perovskite solar cells (PSCs) suffer output efficiency degradation during indoor low light operation (100 lux) due to dynamic internal resistance. This work proposes a constant voltage reference method (CV-RM) with dynamic impedance matching, enabling wide-illuminance Maximum Power Point Tracking (MPPT) via frequency-impedance co-regulation. Characterization establishes optimal voltage ratio K = 0.8. A digitally tuned oscillator adapts charge pump frequency (0.11-2.58 MHz) to match PSCs resistance. The all-analog design achieves MPP voltage locking, eliminating ADCs and digital processing. Experiments demonstrate: 100 lux cold start, full-range coverage (100-1000 lux), and cost reduction for billion-scale IoT deployments.

To address rare-earth dependency in PMSMs and low torque density in synchronous reluctance motors, a permanent magnet reluctance dual-rotor motor is proposed. A collaborative genetic algorithm optimizes a 7.5 magnetic bias angle and the parameter scanning method is employed, reducing cogging torque by 90.8 and torque ripple by 11.1. A hierarchical control scheme uses hysteresis control for current loops, a torque distribution algorithm is introduced to address the coupling issue between the dual rotors, and adaptive sliding mode control for speed loops. The rotational speed overshoot is constrained within 2, achieving 0.05 response, and reducing chattering. Simulations validate the method.

This paper introduces a power management circuit (PMC) designed for energy-harvesting (EH) based IoT devices. The proposed PMC combines the benefits of single-capacitor-based power storage and a unit with adjustable charging and discharging thresholds. The single-capacitor-based design significantly reduces the area of power storage and its switch transistors compared to conventional multiple-capacitor-based designs. The threshold adjustable unit minimizes the energy wasted in power transmission and provides energy for the useful process in the EH-based IoT device, accelerating the processing. The proposed circuit is implemented using the TSMC 65 nm process. Post-layout simulation results in HSPICE show that the power management circuit occupies only 1.01× of the area of the conventional smallest circuit while reducing the average processing time of the PMC-managed IoT load by 18.8%.

In this paper, we propose a new wideband microstrip phase shifter based on an RF transformer. The structure consists of two main components: a mainline and a reference line. The mainline is a bandpass filter that incorporates the coupling characteristics of the RF transformer to achieve the required bandwidth. The reference line is a uniform transmission line, and its electrical length is adjusted to control the phase shift. Compared to traditional phase shifters, this design offers several advantages, including a wide bandwidth, compact size, simple structure, and a large phase shift range. To demonstrate the effectiveness of the design, a phase shifter with a 90°-225° phase shift range was both designed and simulated. Additionally, a 90° phase shifter was fabricated and measured. The measurement results show that the phase shifter achieves a phase shift of 90° ± 2.1°, with an S11 of less than -10dB and a fractional bandwidth (FWB) of 63.25%.

This paper presents a synthesizable quarter-rate CDR based on a fractional-N ADPLL, designed in a 28-nm CMOS process for 32 Gb/s operation. The architecture integrates a quadrature rotational frequency detector (Q-RFD), a bang-bang phase detector (PD), and an N-filter to enable robust frequency acquisition and fine phase alignment. Post-layout simulations confirm locking from a 30,000 ppm frequency error within 11 μs and residual frequency error below 50 ppm. The design achieves 1.3 ps RMS jitter and occupies less than 0.016 mm², offering strong PVT robustness and suitability for high-speed serial links.

This paper proposed back propagation neural network (BPNN)-based design of digital analysis filters to cancel the aliasing errors caused by the non-ideal characteristics of analog mixers and filters in hybrid filter bank digital-to-analog converter (HFB DAC). Initially, we establish a mathematical model for HFB DAC to derive the ideal and actual transfer functions, which is used to calculate the estimation error between the ideal and actual transfer functions. Then, the approximation error is obtained by summing the real and imaginary parts of the estimation error. Finally, the BPNN is used to minimize the approximation error, thereby obtaining the optimal coefficients for digital analysis filters to achieve the aliasing errors cancellation. In addition, this paper derives the computational complexity of BPNN. The simulation results show that our proposed BPNN-based design of digital analysis filters achieves better aliasing errors cancellation than the weighted least squares (WLS)-based, WLS+Optimization-based and minimax using second order cone programming (SOCP) designs at the cost of increased computational complexity.

This paper proposes a new type of embedded thermal pipe and thermal sheet (T-P&S) combined high power density PCB thermal structure for the problems of poor thermal conductivity and uneven thermal resistance distribution of the traditional PCB structure. A special thick copper thermal layer is constructed inside the traditional PCB, and low impedance thermal paths are established between the heat generating layer and the heat dissipation layer through the upper and lower thick-walled thermal pipes to realize a good heat exchange. Among them, the thermal conductivity layer and the signal layer are insulated to avoid thermoelectric coupling, which affects the electrical characteristics of the device. And with the traditional PCB heat dissipation structure for comparative experimental study, the experimental results show that, in the same thermal power, the designed PCB structure compared to the traditional PCB device surface temperature reduced by 5 ℃, synchronous reduction of 11%. Through the long-term application of thermal power experiments, it is concluded that the proposed structure HPD-PCB (T-P&S) can effectively and improve the uniformity of thermal stress distribution and reduce the steady-state thermal temperature of high-power devices.

Adder neural networks (AdderNets), a promising lightweight alternative to traditional CNNs, face the “memory wall” challenge in von-Neumann architectures. Computing-in-memory (CIM) has emerged as a promising solution to address this memory bottleneck. This work proposes a novel spin-transfer torque magnetic random-access memory based digital-CIM macro tailored for AdderNets mapping, leveraging Boolean logic-optimized architecture to seamlessly integrate storage and computation. The architecture is validated through simulations under 40 nm CMOS technology. Results show that the architecture achieves an energy efficiency of 39.48 TOPS/W in 8-bit network inference, representing a 1.4× to 2.0× improvement over state-of-the-art digital CIM designs.

Audio noise suppression techniques are commonly utilized across diverse audio systems,often relying on general-purpose processors. However, this leads to inefficiencies in terms of hardware resource usage, energy consumption, and overall system expense. This paper presents a specialized microcontroller for audio noise suppression,based on the Hummingbird E203 framework. Key hardware optimizations include enhanced multiplication and division units using Booth4 encoding, Wallace tree, and dual SRT-4 mechanisms, alongside the integration of an F instruction set for floating-point operations. A camouflage strategy reduces memory transaction complexity. Software improvements utilize adaptive spectral subtraction for efficient noise suppression. Benchmarks show a 4002.5% boost in floating-point performance and significant gains in noise reduction, with a 54.6% decrease in noise energy and a 28.7% rise in signal-to-noise ratio, highlighting its efficacy.

In low-voltage servo systems powered by batteries, as the battery continues to discharge and the system enters an under-voltage condition, the PMSM's torque becomes limited due to the saturation of back electromotive force during motor startup. Additionally, in steady-state operation, the output torque is constrained. To address these issues, a novel control strategy is proposed that combines the Quasi-Z-source network with the low-voltage servo drive. The rate of change of the phase current amplitude of the PMSM is introduced as a compensation factor into the voltage loop control of the Quasi-Z-source network. This approach enhances the DC bus voltage and its dynamic response performance, thereby improving the motor's output torque. Consequently, the proposed strategy effectively improves the system's response speed and output capability under battery under-voltage conditions.

Logic locking is a technique designed to safeguard integrated circuit netlists from security threats. However, recent advancements in machine learning-based structural attacks have significantly challenged existing logic locking methods. Moreover, current defenses against these structural attacks often diminish the resilience of logic locking against Boolean satisfiability-based attacks (SAT attacks). To address this limitation, this paper presents the Depth-Coupling Logic Locking (DCLL) technique. DCLL utilizes a key to control a multiplexer and an XOR gate, establishing a robust interconnection at the functional level. By incorporating subgraph replacement, DCLL enhances both the locking mechanism and its resistance to SAT attacks. Experimental results reveal that DCLL achieves an exponential increase in SAT attack resistance while maintaining robustness against machine learning-based removal attacks. Furthermore, DCLL provides a balanced defense against oracle-guided (OG) and oracle-less (OL) attacks. For circuits with one million gates, DCLL incurs minimal overheads of 0.37% in area and 0.40% in power, positioning it as an efficient and effective solution for enhancing the security of logic locking techniques.

A 16-bit 210MSPS pipelined analog-to-digital converter (ADC) with distributed differential reference voltage buffer (DDRVB) and for-ground calibration is presented. Current summing and floating current control techniques are used in DDRVB to achieve high precision adjustable reference voltage. In order to improve the power supply rejection ratio (PSRR) and reduce the output impedance and power consumption, the push pull output and replica circuit structure is introduced. A mix-signal for-ground calibration method for pipelined ADC is proposed. Offset, gain and mismatch errors in pipelined sub-stage circuits can be compensated by the proposed calibration method. Based on the proposed DDRVB and calibration method, a prototype 16-bit 210MS/s pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. Test results show, the 16-bit 210MSPS ADC core achieves the signal-to-noise ratio (SNR) of 77.3dB and spurious free dynamic range (SFDR) of 101.7dB, with 5.1MHz input at full sampling speed, while consumes the power consumption of 495mW.

CLLC converters are widely used in bidirectional DC applications, particularly in aviation and vehicle power supplies, requiring high dynamic commutation performance. This paper presents a commutation control method for CLLC converters based on a state trajectory model. The forward and reverse state trajectory models are developed, and the optimal commutation trajectory is derived. The gate drive signal's pulse width is calculated based on the post-commutation gain. Simulations validate the proposed model's accuracy and the control method's dynamic performance, showing significant improvement over traditional linear control methods.

This paper reports p-channel metal-oxide heterostructure field-effect transistors (MOSHFETs) based on p-GaN/GaN/Al_0.29Ga_0.71N heterostructures grown by metal-organic chemical vapor epitaxy (MOCVD) on Si substrates. The two-dimensional hole gas (2DHG) density in the p-GaN/GaN/Al_0.29Ga_0.71N heterostructures is 1.3×10¹³ cm^-2 and remains unchanged down to a temperature of 80 K. A reduction of the GaN channel thickness by dry etching renders the p-channel MOSHFET enhancement-mode (E-mode) with a negative threshold voltage (V_th). The E-mode p-channel MOSHFET realized by GaN (18 nm)/Al_0.29Ga_0.71N shows a threshold voltage V_th of -0.79 V, an on-current |I_ON| of 2.41 mA/mm, a low off-state drain-source current (|I_OFF|) of 2.66×10^-9 mA/mm and a low subthreshold swing (SS) of 116 mV/dec. Such ultralow |I_OFF| and SS indicates high-quality epitaxial material. The high-temperature operation capability of the p-MOSHFET is evaluated up to 200 °C.

To meet the demands of 5G base stations in large PAPR signal environments, this paper presents the design of a 550W improved three-stage Doherty power amplifier with a 12 dB back-off range. GaN HEMT devices with gate widths of 18 mm, 27 mm, and 27 mm are selected for internal matching design to ensure ultra-high output power. The paper analyzes the active load modulation mechanism under an asymmetric architecture and proposes an impedance matching design method suitable for this configuration. Test results in the 2.5-2.7 GHz show that the linear region gain is between 10.5 and 13.4 dB, the saturated output power ranges from 57.2 to 57.6 dBm, and the saturated drain efficiency is between 69% and 73%. At a 12 dB power back-off, the drain efficiency is between 55% and 58%. When the power back-off is 6 dB, the drain efficiency ranges from 62.2% to 65.1%. After incorporating Digital Pre-Distortion (DPD) technology, the ACPR test result is -55.9 dBc. These results address the issues of insufficient back-off range and linearity degradation due to saturation, which are common in traditional three-way and three-stage Doherty power amplifiers.

In this paper, a smart system monitoring sensor based on a 12-bit SAR ADC with hybrid DAC is presented, and fabricated in a standard 55-nm CMOS process. By utilizing a MUX to switch the input channel, monitoring of the temperature and voltage at critical points is achieved. Additionally, a double conversion method is also proposed for circumventing the current mismatches of the two BJT temperature sensing elements, thereby lower the circuit complexity. For temperature sensing, the sensor shows a measured inaccuracy of ±1.5℃ from -55℃ to 125℃ with an resolution of 0.86℃. For voltage sensing, the ADC shows a measured DNL and INL of +0.43/-0.47LSB and +1.4/-1.1LSB, respectively. Thanks to the proposed technique, the sensor consumes low power of 182μW under a 1.8/1.2V supply at a conversion speed of 156kS/s, and occupies an area of 0.074mm².

Mel-frequency cepstral coefficients (MFCC), an FFT-based speech feature extraction (FEx) algorithm, is a significant power consumer in low-power keyword spotting (KWS) chips. This work presents a KWS chip with an energy-efficient FEx, with an expanded-3bit-twiddle FFT (E3bT-FFT) algorithm which reduces power of FFT by 5.7x. Meanwhile, a multiplier-free MFCC (MF-MFCC) is proposed, effectively eliminating power-hungry multipliers and reducing the MFCC computational load by 7.3x. Fabricated in a 65-nm CMOS process, the chip occupies 0.17 mm² and consumes 2.3 µW, with the computation unit in FEx consuming just 76 nW, and achieves 94.9% accuracy on a 1-Word KWS with Google Speech Commands dataset (GSCD).

In this paper, an Efficiency Optimization Strategy (EOS) is proposed to address the issue of low efficiency in the Dual Active Bridge (DAB) DC-DC converter across certain power ranges under wide voltage conditions, with the aim of further enhancing the converter's efficiency over a broad operating range. First, in the low power range, a phase-shift control strategy is introduced, which enables wide-range Zero Voltage Switching (ZVS) and near-optimal inductor current RMS values. Through this strategy, ZVS is ensured for all switches under light load conditions, while under medium load conditions, ZVS is lost for only two switches. Subsequently, in the high power range, the optimization target is smoothly transitioned to the optimal RMS current value by utilizing the natural ZVS characteristics of the DAB converter. The operating range of the EOS is effectively extended, further reducing current stress and RMS current values, thereby achieving global efficiency optimization of the DAB converter. Finally, an experimental platform is constructed for verification, and the correctness and effectiveness of the theoretical analysis are confirmed by the experimental results.

In this work, gate leakage behavior on Schottky-type p-GaN gate AlGaN/GaN HEMT is investigated, especially when the Schottky junction is damaged. A controllable degradation of the Schottky junction is achieved, then the previous semi-floated p-GaN is electrically connected to the gate electrode. Therefore, the pre-stressed GaN device exhibits an improved gate stability, as well as a normal gate control and large gate swing. Furthermore, the associated trap level is extracted by Arrhenius plot based on the exponential relationship between the recovery speed versus temperature.

This paper presents a transparent super-wideband (SWB) MIMO antenna based on a metal mesh structure. The metal patch and substrate of the antenna are hollowed out, resulting in a transparency of up to 77% and a radiation efficiency exceeding 82%. The bandwidth of this MIMO antenna ranges from 1.6 to 19.2 GHz, achieving a bandwidth ratio of 12: 1. An engineered parasitic decoupling structure ensures that the isolation between antenna elements is greater than 25 dB, and the envelope correlation coefficient (ECC), diversity gain (DG), channel capacity loss (CCL), and total active reflection coefficient (TARC) all reach good values.

In this paper, an improved coverage optimization method for video sensor networks(VSNs) based on Whale optimization algorithm (SGWOA) is proposed to solve the problem of uneven distribution of nodes in random deployment of video sensor networks, which will cause coverage holes or coverage redundancy in the coverage area of VSNs. Firstly, Sobol sequence is used to initialize the population, which improves the diversity of the population and makes the distribution of network nodes more uniform when randomly deployed. Secondly, the nonlinear convergence factor and adaptive inertia weight are introduced to prevent the algorithm from falling into local optimal prematurely. Finally, Levi's flight strategy is added to disturb the position update during whale optimization, which speeds up the convergence of the algorithm and avoids premature convergence.

Due to the low noise and high linearity characteristics of GaAs Hetero-junction Bipolar Transistors (HBTs), Low Noise Amplifiers (LNAs) are widely used in aerospace, communication, computer, and other fields. Extracting device model parameters is of great significance for subsequent research on the electromagnetic compatibility characteristics of such devices. In this paper, based on the small signal model, the model parameters of the amplifier are extracted by combining the I-V characteristics of the amplifier under different external voltage conditions. The linear model parameters are extracted using a fitting analysis method to obtain the Pspice circuit model of the GaAs amplifier under normal operating conditions. The simulation results align closely with the measured results. Compared with traditional modeling methods, this approach effectively resolves the issue of being unable to measure parameters due to chip packaging. This method holds substantial significance in extracting circuit model parameters and conducting in-depth research on circuit electromagnetic compatibility characteristics of this device.

Level-increased nearest level modulation (NLM) has been widely used in the modular multilevel converter (MMC) due to its simple implementation and low switching frequency in recent years. However, there are some disadvantages such as the poor performance of output voltage distortion and harmonic circulating current. A harmonic circulating current (CC) suppression method based on level-increased NLM is proposed in this paper. The impact of level-increased NLM on the CC is firstly analyzed. Then, a 5-voltage-level compensation method for harmonic CC suppression is proposed. Simulation and experiment verify the effectiveness of the proposed method.

A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency ( f_T). Broadband operation is achieved using an enhanced degenerated Darlington f_T-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional f_T-doubler structures, the enhanced cascode Darlington f_T-doubler structure reduces the “V_CE mismatch” between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher V_CE for amplifying transistors, which represents higher f_T,_peak performance. Benefiting from the proposed Darlington f_T-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181- f_T bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

To improve the dynamic response performance and robustness of a permanent magnet linear synchronous motor (PMLSM)-based servo system, an adaptive proportional-integral-derivative (PID) controller based on a particle swarm optimization neural network is proposed. First, according to the mechanical dynamics equation of the PMLSM, a mathematical model of the PMLSM was established. Second, an adaptive PID speed controller is designed to realize real-time control of the PMLSM. To improve the dynamic performance and stability of the controller, a particle swarm optimization neural network is used to dynamically tune the parameters. Finally, the effectiveness of the proposed controller was verified on the MATLAB/Simulink simulation platform. Compared to the traditional PID controller, the adaptive PID controller can improve the dynamic performance of the system more effectively.