A digital multiplier circuit module is proposed, which is cascadable to perform multiplication for any word length, without the use of external circuitry. The number of cascaded modules can be changed dynamically, so that it is useful for designing a system, where many high speed multiplications and less speed but high precision multiplications coexist, as in the application to robot control or image processing.
The soundness of the circuit was confirmed by making one-chip integrated multipliers, and no drawbacks are expected if it is used as macro cells in VLSI.
No other method can compare with the parallel multiplier for speed, but to multiply numbers with digits beyond the chip capability, it is necessary to prepare not only several parallel multipliers but also external circuitly.
Such an experience is what we encounter due to change of specification or application environment. The proposed method is useful to cope with such problems.

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The Hall effect multiplier has a Hall generator which is placed in an air gap of the exciting magneticcircuit. The multiplier output is given as a voltage proportional to the multiplication of Hall current andexciting current. Described in this article are the properties of Hall effect multiplier such as geometry, internal resistance, gain and accuracy of multiplication and temperature variation of output voltage. Themultiplier is in such design as to be applied to watt-onverter, multiplier/divider, square-oot computer, etc. of this multiplier, there are three types, one using the ferrite pot magnetic cores and the other twousing the laminated permalloy cores which are punched in EI shape. Each multiplier has a Hall generatormade of germanium cristal. In this germanium, the antimony is doped in optimum concentration so thatthe best multiplication gain and temperature characteristics are obtained. As an application of this Hall multiplier, the characteristics of watt-onverter is given in appendix.

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With the expectancy of higher performance of digital systems, the multiplier with both higher speed and higher precision is required as a key factor of the system improvement. On the other hand, it is quite common that these digital parts are assembled as a system LSI, and in this case, it is essential that these parts are re-usable as a core. The answer to this requirement is modularizing, which can cope with the variable precision, not a fixed one, as a multiplier structure.
The structure proposed here can perform a multiplication by cascading necessary number of the same modules and by repeated usage of the modules with necessary clock cycles. By this method, much higher speeding up compared to the conventional sequential type, as much as limitless multiplication precision compared to the parallel type, can be obtained.

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Recently it seems that there are almost no multipliers using Hall elements. This fact mainly comes from the magnetic nonlinearity such as magnetic saturation and hysteresis of a magnetic core used in order to increase the gain of the magnetic flux path.
This paper shows realization of a high precision multiplier using a Hall element with magnetic flux control. Moreover, the relation between the precision of the flux control and the precision of the multiplier is clarified. As a result, it is shown that the precision of the proposed multiplier is considerably higher than that of a existing IC multiplier.

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Redundant binary representations diminish the latency of addition at moderate hardware cost and thus can play an important role in processor design. Usually it had been overlooked that the choice of good representation for digits is of crucial importance to high speed and efficient implementation. Due to inadequate representation of digits, implementation of adders for redundant binary representations has been insufficient at speed.
In this paper we propose a high-performance redundant binary adder using a new hybrid representation method, which attempts to represent each digit by hybrid 2 bits/3 bits. This purpose is to present a compromise between the high speed of representing each digit by 3 bits and hardware-efficiency of representing each digit by 2 bits. By using the PARTHENON, a CAD system for VLSI, this adder is designed and evaluated. As a result, the proposed adder requires lower power dissipation, more efficient area, and about 1.4 times speed as compared with the conventional redundant binary adder. Finally, this proposed adder is applied to the multiplier and the availability is shown.

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The paper proposes a method of digital parallel divider circuit module and its one-chip integration. The multiplication and division are performed very frequently in computers, electronic control systems, signal processing for sound, and image processing. So far, we have proposed a new module of multiplier and divider, which is easily cascadable to perform arithmetic for any word length, without the use of external circuitry. As the multipliers are used more frequently, many fast multipliers with high precision have been proposed and integrated. But there are few one-chip dividers, because they are available only within the limited word length of dividend. So that, there are few merits of making one-chip integrated dividers.
The proposed parallel divider circuit module is cascadable on dividend for any word length, without the use of external circuitry. The soundness of the circuit was confirmed by computer simulation.
We can design a system without the restriction of the bit length of dividend by using this divider. The proposed method makes it possible to implement one-chip integrated dividers suitable for fast division for any word length.

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本論文では、バックゲート駆動弱反転領域動作型トランスリニア原理を用いた新たなアナログを提案する。提案するでは、従来のトランスリニア原理を用いたものより低電源電圧および低消費電力で動作し，かつ従来回路同様に温度変化やデバイスパラメータに対して低感度な回路構成となっている。加えて適応バイアス技術を用いることでミスマッチによるバイアス電流の差異を吸収し、出力波形への歪みを低減することができる。

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Demands of minimization of digital signal processor, and reduction of power consumption have been rised in recent years. From these demands, high performance multiplier has to be developed for designs of digital filter and video transmission LSI. In this paper, we compare various multipliers by the hardware description language, and design FIR filter based on the above result.

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一般にPCMシンセサイザの楽音生成系における信号処理は乗算を含む。そのためPCMシンセサイザをハードウェアで実装する際には,多ビット高速が必要である。本稿ではパルス密度変調(PDM)方式による1ビット信号処理の単純性に着目し,従来のPCMシンセサイザにΔΣ変調器を導入することで,をより単純な別の回路にて代替する手法を検討した。再設計したシンセサイザはシミュレーションによって動作を確認し,その出力音を原型のPCMシンセサイザと比較した。

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We designed a VLSI (Very Large Scale Integrated circuit) chip of FFT multiplier using a floating-point representation with optimal data length based on an experimental error analysis. Using the hardware implementation, we can perform 2^5 to 2^<13> hexadecimal digit (39 to 9,831 decimal digit) multiplication 25.1 to 45.6 times (33.9 times in average) faster than using FFTW3, at an area cost of 9.05mm^2. The hardware FFT multiplier has 64 times faster performance than exflib (a multi-digit arithmetic library using Karatsuba method) for longer than 2^<21> hexadecimal digit (≒2,520,000 decimal digit) multiplication. Considering the wide applications of its FFT modules, the performance and cost of the FFT multiplier justifies the VLSI implementation.

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Photoelectric chopper operates on the principle of modulating a light source which is used to illuminate photoconductive cells. That is, each of the two cells arranged in the chopper is illuminated alternatively by each half cycle of the light generated by a driving AC voltage. At the same time the cell changes its conductance into on-off action like a switch, so AC output voltage may be obtained in the load resistance connected to each cell. The chopper has such advantages as nonmechanical contact and low drift noise, and is nearly equal to mechanical chopper in many circuit applications. The chopper, however, has a restriction caused by the following limited factors. The first is an imperfect switching action. The cell conductance, even when brightly illuminated, never approaches infinity, while even when dark, never zero. Then, the ratio of light and dark conductances in the steady state may approaches 10⁶. The second is a time lag of the cell conductance in response to a change in light level. These limited factors tend to restrict the modulating frequency, input and output impedances because conversion gain and phase lag of the chopper depend on these factors. The effect of these factors on conversion gain and on phase lag was theoretically analyzed and designing formula for the chopper was obtained. The formula was experimentally authorized. The authors developed photoelectric chopper driven by AC 115V (50c/s) for low level instrument. They have about 87% of conversion efficiency compared with mechanical chopper, 30 degree phase lag to driving voltage, 1μVrms drift noise and 250kΩ input impedance.

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本論文では、超音波領域で有効に使用できる乗算型高周波電力計の概要と特性について報告する。この電力計は電子回路において、電力が電圧、電流及びその力率の積で表わされることに注目して設計されている。この電力計を使うことによって、従来の超音波電力計では測定の困難であった高インピーダンスの負荷、例えば10kΩのインピーダンスを持つ負荷に1kWの電力を与えた場合、端子電圧は約2kVの高電圧となるが、このような負荷に対しても有用であり、しかも10MHzまでの高い周波数領域まで測定可能となった。また、力率を考慮に入れたため、歪波や力率の悪い信号に対しても使用可能である。更に、電圧、電流プローブに改良を加えることによって、測定時に負荷の回路を切断することなく電力の測定ができる。

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我々は今まで，小型で広帯域な円偏波アンテナの実現を目的として，マイクロストリップアンテナと二重平衡型を複合した新しい原理に基づく円偏波アンテナを提案している．本アンテナは，アンテナ素子にダイオードをスター状に接続して二重平衡型を構成し，バイアス電圧を制御することによってダイオードの非線形性を利用して直交する２つのモードに90の位相差をつける事ができ，その結果円偏波を実現することができる．さらに，バイアス電圧の極性によって円偏波の右旋/左旋の切り替えが可能となる．本稿では試作アンテナにより，アンテナの非線形特性についての実験的検討を行い，入力電力の変化によって円偏波アンテナとしての特性が変化することが分かった．

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In this paper, we propose a new modulo multiplier suitable for repeated operations using redundant representations. First, we consider a computation rule for radix-2 modulo multiplications. In radix-2 operation, we show two methods to calculate (2^i-1 mod n) from (2ⁱ mod n) and decide product digits sequentially from upper side. These methods make it possible to perform (2^i-1 mod n) and multiplications simultaneously. Second, we attempt to apply these methods to radix-4 operations which enables us to reduce clock cycles by only shift and sign change. We propose some structures to perform each part efficiently for radix-4 modulo multiplications. The high-speed redundant binary adder/subtractor which we have already proposed is applied to these structures. By using this adder/subtractor, the longest delay path of this modulo multiplier becomes very short. Finally, by using PARTHENON which is a design system for VLSI, this modulo multiplier is designed and evaluated. As a result, we show the speed of this proposed modulo multiplier becomes over 2.5 times as compared with the conventional structures.

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