Under a strong radiation environment such as decommissioning situation of nuclear power plants, radiation-hardened processors are required for robots and other systems. Currently, space-grade processors are available. However, currently available space-grade processors are always weak for radiation and the life-time of the space-grade processors is limited to an extremely short period. So, we have introduced triple modular redundancy (TMR) for

-V processor to increase the total-ionizing-dose tolerance. This paper presents a triple modular redundancy -V processor design. In the -V processor, majority voting operations are executed automatically at every clock cycle. The -V processor was implemented onto a Cyclone-V Field Programable Gate Array (FPGA) on a DE1-SOC FPGA board. It has been confirmed that the -V processor can work correctly. Additionally, the maximum operating clock frequency was measured as 64.82MHz. The FPGA’s resource usage was 45%.

抄録全体を表示

The constructed Nuclear Power Plants in China have mainly adopted Deterministic analysis to implement categorization of structure, system and components. However, considering the balance of economy and safety, there are some inappropriate in the existing categorization of structures, systems and components. With the development of Probability Safety Assessment (PSA) and the application of Risk-Informed technology, a comprehensive approach which combines deterministic and probabilistic analysis and criteria has been proposed. According to 10.CFR 50.69 and RG 1.201, which are from the perspective of Probabilistic analysis, this paper categorizes systems and components into Safety Significant and Low Safety Significant by their safety degrees. Integrated with traditional deterministic categories, it has formed four different safety-classes which are -1, -2, -3 and -4 respectively. As for those -3 components, the risk-informed categorization process determines that they are not significant contributors to plant safety. Therefore, special treatment requirements are removed for -3 components and replaced with high-level requirements, to reduce unnecessary regulatory burden and budget cost and to improve economics of plants. In this paper, for instance, we will choose two typical systems of Fuqing NPP in China to implement the risk-informed categorization. And finally, conclusions can be drawn and optimization of existing categorization can be got.

抄録全体を表示

RNA-induced silencing complex () はRNAサイレンシングによる遺伝子の転写後発現抑制やウイルスRNAの分解等において中心的な役割を果たすリボヌクレオタンパク質複合体である。はコア因子としてARGONAUTEファミリーに属するタンパク質(AGO)と一本鎖の低分子量RNAを含むことが知られているが、これまで植物では無細胞形成系が確立されておらず、その形成過程を生化学的に解析することができなかった。本研究で我々はタバコ脱液胞化プロトプラスト抽出液(BYL)を用いてAGO1と22ヌクレオチドの合成二本鎖siRNAからを形成させる実験系を確立した。BYLにおける形成において、二本鎖siRNAはAGO1にATP、Mg²⁺、さらに分子シャペロンHSP90依存的に取り込まれ、続いて二本鎖siRNAのパッセンジャー鎖はAGO1のRNase活性依存的に取り除かれた。形成されたはガイド鎖のsiRNAと相補的な配列を含む標的 RNAと結合しそれを切断した。

抄録全体を表示

Radiation tolerant optically reconfigurable gate arrays (ORGAs) have been developed [1]-[5]. These radiation-tolerant optically reconfigurable gate arrays have two characteristics: high total ionizing dose and soft error tolerance and fast reconfiguration. To improve the performance of radiation-tolerant optically reconfigurable gate arrays, we proposed the Mono Instruction Set Computer (MISC). MISC is a processor architecture that reduces the number of instructions to one by relying on reconfiguration of the circuit with programmable devices to change functions. As a result, MISC can be implemented in a small gate array area and can provide a higher clock frequency than

(Reduced Instruction Set Computer), which is currently widely used as a processor architecture. In addition, since the implementation area is small, performance can be improved by implementing multiple MISC processors in parallel in the same area as a processor. In this study, we implemented the arithmetic part (ALU) of a 4-bit MISC processor with six functions (logical AND, logical OR, addition, subtraction, multiplication, and division), and compared and evaluated it with an implemented processor. The results confirm that MISC processors have higher performance than processors. In addition, a 32-bit MISCALU was implemented and its performance was verified with maximum operating frequency and footprint

抄録全体を表示

We believe that personal robots like current personal computers will be used in an office and at home in the near future. And we have already designed function-classified parallel computer architecture for personal robots: ASPIRE (ASynchronous, Parallel, Interrupt-based, and REsponsive architecture) . In this paper, we design and implement the personal robot ASPIRE-II based on ASPIRE using processors. Many researchers think that processers are not suitable for embedded application due to the pipeline hazards, and the loads and stores of a large number of registers in case of interrupts. However we dare to apply prosessers (SPARC family) to ASPIRE so as to have both high computing performance and good interrupt capability. Definitely, we apply register windows of SPARC architecture to ASPIRE. We also describe the efficiency of the architecture by evaluating ASPIRE-II.

抄録全体を表示

Posttranscriptional gene silencing (PTGS, RNAサイレンシングのひとつ)では、mRNAやウイルスRNA等がRNA-induced silencing complex ()の標的RNAとして、翻訳抑制や切断を受けて不活性化される。にはARGONAUTEファミリーのタンパク質(AGO)と一本鎖の小分子RNAが含まれ、小分子RNAが相補的配列を含む標的RNAを認識する。形成はPTGSの誘起段階として重要であるが、その分子機構については未だ明らかでない点が多い。これまでに我々は、脱液胞化タバコプロトプラスト抽出液(BYL)を用いた植物の無細胞形成系を確立し、本系を用いた解析により、二本鎖の小分子RNAがAGO1に結合する段階に分子シャペロンHSP90が関与することを示唆した。今回我々は、HSP90とAGO1と二本鎖小分子RNAを含む複合体が形成され、HSP90がATPを加水分解すると、AGO1と二本鎖小分子を含む複合体からHSP90が分離し、AGO1に結合している小分子RNAの一本鎖化が起きること、さらに、この過程にHSP90のコシャペロンが関与することを示す。

抄録全体を表示

-V processors have been widely used in recent years due to their open architecture. In addition, in the field of embedded systems, a small area on an integrated chip is desired from the viewpoint of cost reduction. Therefore, we will use the compressed instruction set defined for -V to develop a small-area embedded processor. By adopting a compressed instruction set, the size of all parts that could be changed from 32 bits to 16 bits was reduced. As a result, we clarified that there are problems such as the overhead required to implement compressed instructions and insufficient compiler optimization.

抄録全体を表示

This study assessed relational-interdependent self-construal （

）, acculturative stress, and social support of Chinese and American students studying in Japan via a quantitative study.

Four hundred and thirty-one participants were surveyed in the current study. Among them, 159 were Japanese college students （42 males and 117 females, age: M＝19.84, SD＝2.69）, 171 were Chinese students studying in Japan （42 males and 129 females, age: M＝19.84, SD＝2.69） and 101 were American students studying in Japan （40 male and 61 females, age: M＝22.72, SD＝4.53）. Relational Interdependent Self-construal Scale, Acculturative Stress Scale for International Students, and Index of Sojourner Social Support were used as instruments.

Chinese students scored significantly higher on

than both Japanese and American students, but American and Japanese students did not differ significantly regarding . Consistent with previous findings, American females scored highly on than American males. As a significant predictor of acculturative stress for American female students, Japanese language proficiency benefits their adjustment to a society with a different culture. However, the significance did not appear in Chinese students.

The most noteworthy finding in this study is that for female students, higher

predicted higher acculturative stress. In particular, the finding is notable for Chinese female students. Another remarkable point is that for Chinese female students, those with higher levels of Japanese language proficiency are more likely to obtain more social support.

抄録全体を表示

In Internet of Things (IoT) applications, system-on-chip (SoCs) with embedded processors are widely used. As an embedded processor,

-V, which is license-free and has an extensible instruction set, is receiving attention. However, designing such embedded processors requires an enormous effort to achieve a highly efficient microarchitecture in terms of performance, power consumption, and circuit area, as well as the design verification of running complex software, including modern operating systems such as Linux. In this paper, we propose a method for directly describing the RTL structure of a pipelined -V processor with cache memories, a memory management unit (MMU), and an AXI bus interface using the C++ language. This pipelined processor C++ model serves as a functional simulator of the complete -V core, whereas our C2RTL framework translates the processor C++ model into a cycle-accurate RTL description in the Verilog-HDL and RTL-equivalent C model. Our processor design methodology using the C2RTL framework is unique compared to other existing methodologies because both the simulation and RTL models are derived from the same C++ source, which greatly simplifies the design verification and optimization processes. The effectiveness of our design methodology is demonstrated on a -V processor that runs Linux OS on an FPGA board, achieving a significantly short simulation time of the original C++ processor model and RTL-equivalent C model in comparison to a commercial RTL simulator.

抄録全体を表示

Emerging image and video applications and conventional MPSoC architectures encounter drastically increasing performance and flexibility requirements. In order to display high quality images, large amount of image processing needs to be carried out. These image processing algorithms are nonstandard and vary case by case, and it is difficult to achieve real time processing by using general purpose processors or DSP. In this paper, we present two reconfigurable Application Specific Instruction-set Processors (ASIP) which can perform several image processing algorithms by using the same processor architecture. These ASIPs can achieve performance similar to DSP; meanwhile, while the area is considerably smaller than DSP and slightly bigger than conventional processor. 1D ASIP can perform 16 times higher compared to a processor, and 2D ASIP can perform 3 to 7 times higher compared to a processor.

抄録全体を表示

-V is a based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in -V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.

抄録全体を表示

It is known that Haloxylon has successive cambia and its radial growth rate is not clear as indicated by the fact that the annual boundary cannot be determined by dendrochronological approach. Radial increment through successive cambia () layers possess similar morphological feature as compared to annual rings by megascopic cross sectional observations. Previous studies have demonstrated that the dendrochronological methods cannot be applied to some species that possess successive cambia. The objective of the present study is to clarify the growth rate of layer in Haloxylon ammodendron by a series of radiocarbon dating. Two H. ammodendron specimens (S1 and S2) were collected from the southern edge of Gurbantünggüt Desert in Northwestern China. Radiocarbon measurements revealed the numbers of annual layer to be 2.98 ± 0.51 (S1) and 3.65 ± 0.53 (S2). Linear regression shows a strong relationship between growth period (x) and radial increment accumulation (y): y = 1.52x + 0.76 (R² = 0.96, P < 0.001) for S1 and y = 1.70x + 4.49 (R² = 0.94, P < 0.001) for S2, respectively. Anatomical observations on the layer using scanning electron microscope (SEM) image showed that: (1) the early wood and late wood were not present or differentiated; (2) axial vessel groups (about 2-10 vessels) are often distributed in the bark-side; and (3) sclerenchyma cells as junctions tightly adhered vessel groups at outside in each layer. These observed features are completely different from those in annual ring morphologies. We tentatively hypothesize that these features are due to the formation of multiple layers within one growing season in order to aid in water storage in the stem to survive in harsh habitat conditions. This research will help further the knowledge in the physiological and ecophysiological researches on H. ammodendron and other successive cambia species.

抄録全体を表示

This paper implements an execution unit that generates grid square codes from latitude and longitude on a -V processor and evaluates its performance. In recent years, a statistical analysis which uses grid square codes has been focused. Although grid square codes are obtained from latitude and longitude based on several equations, this calculation requires a long computing time because it needs a lot of floating-point instructions. In this paper, an execution unit which generates grid square codes from latitude and longitude is designed, and the instruction which generates grid square codes by using the unit is implemented on a -V processor. The proposed execution unit can generate the corresponding grid square code from latitude and longitude in one cycle. As a benchmark, a program that counts the number of times the randomly generated latitude and longitude match the specified grid square code is used. Experimental results show the in-order -V processor with the proposed unit which implemented on an FPGA achieves a 36.6% reduction of execution time compared to the original processor. In addition, the performance evaluation of the out-of-order -V processor with the proposed unit by using the gem5 simulator shows a 23.9% reduction of execution cycles compared to the original processor. This paper also designs an execution unit which converts grid square codes to latitude and longitude. We call this conversion ”Grid-to-Degree conversion”. Experimental results show the in-order -V processor with the unit which implemented on an FPGA achieves a 3.65% reduction of execution time compared to the original processor.

抄録全体を表示

For the increasing demands of computation, heterogeneous multicore architecture is believed to be a promising solution to fulfill the edge computational requirement. In FPGAs, the heterogeneous multicore is realized as multiple soft processor cores with custom processing elements. Since FPGA is a resource-constrained device, sharing the hardware resources among the soft processor cores can be advantageous. A few research works have focused on the resource sharing between soft processors, but they do not study how much FPGA logic is minimized for a different pipeline processor. This paper proposes the microarchitecture of four, and five stage pipeline processors that enables the sharing of functional units for execution among the multiple cores as well as sharing the BRAM ports. We then investigate the performance and hardware resource utilization for a four-core processor. We find that sharing different functional units can save the LUT usage to 31.7% and DSP usage to 75%. We analyze the performance impact of sharing from the simulation of the Embench benchmark program. Our simulation results indicate that for some cases the sharing improves the performance and for other configurations worst-case performance drop is 16.7%.

抄録全体を表示

In this paper, a 32-bit

-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm² of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (V_DD) with +1.6-V back-gate bias voltage (V_BB). The best power density of 33.4-µW/MHz is reached at 0.5-V V_DD with +0.8-V V_BB. The least current leakage of 3-nA is retrieved at 0.5-V V_DD with -2.0-V V_BB.

抄録全体を表示