A novel SEU tolerant SRAM data cell design

Abstract

An improved SEU tolerant SRAM data cell design is presented here. The cell enhances the capability of SEU tolerance by creating spatial redundancy of data and virtue of latch design. The results show that our proposed design achieves high resilience to SEU and provides a 300 times increase in critical charge compared to standard 6T cell without much degradation in speed and Power dissipation. It shows that our design is very suitable for applying in high-reliability circuit and system design.