We apply the mode-matching method to the analysis of coplanar striplines surrounded by multilayer dielectrics and lateral conductive shields. Then the characteristic impedances and the effective dielectric constants of various coplanar striplines are calculated based on assumption that the electromagnetic coupling between the lateral shield and striplines could be neglected with a proper condition. Also we verify the accuracy of the mode-matching method compared with the conformal mapping technique.

View full abstract

A novel reverse-conducting insulated-gate bipolar transistor (RC-IGBT) featuring separated freewheeling diode (FWD) and IGBT is proposed. The proposed RC-IGBT with two kinds of anti-paralleled FWDs (PIN and MPS diode) is discussed. The simulation show that the integrated Merged P-i-N/Schottky (MPS) diode can improve the property of the reverse conduction and reverse recovery greatly than the PIN diode, the reason is that a new mechanism is adopted by the Schottky contact of the MPS diode. As the results indicate that the RC-IGBT with MPS diode achieves lower V_R and J_PR when compared to the PIN diode.

View full abstract

An improved SEU tolerant SRAM data cell design is presented here. The cell enhances the capability of SEU tolerance by creating spatial redundancy of data and virtue of latch design. The results show that our proposed design achieves high resilience to SEU and provides a 300 times increase in critical charge compared to standard 6T cell without much degradation in speed and Power dissipation. It shows that our design is very suitable for applying in high-reliability circuit and system design.

View full abstract

To improve stochastic resonance in a single-electron (SE) device, we propose an SE device having hysteretic characteristics. We first demonstrate by analyzing a mathematical model that the correlation coefficient between the subthreshold input and the inverter output is improved by introducing hysteresis into an ideal inverter (NOT gate). To realize hysteresis in an SE inverter, we have designed an SE device having hysteretic characteristics (2ID-FJI) by combining two input discretizers (IDs) and an SE four-junction inverter (FJI). Evaluations of the correlation coefficients prove that the 2ID-FJI can achieve a significant improvement in stochastic resonance.

View full abstract

A pulse skipping modulation (PSM) with adaptive duty ratio (APSM) in buck converter application is presented in this paper. The output voltage of converter is regulated by the APSM controller generating control pulse with multiple duty ratios. The duty ratio is approximately proportional to the square root of the voltage error between output voltage of converter and reference voltage. The experimental results and simulation are well consistent with theoretical analysis. The duty ratio can vary adaptively with the variance of voltage error and load. The APSM modulation technology can regulate output voltage slightly and improve ripple of output voltage especially in light load.

View full abstract

This paper introduces new connecting structure for waveguides. The structure, similar to that of the SMA connector shell, especially shows its advantages for high-frequency and small waveguides. Compared to conventional waveguide connecting structures such as flanges, the proposed structure is easier to connect/disconnect and does not occupy spaces. Additionally, authors clarify that the connection performance of the proposed structure is almost the same as the conventional connecting structure.

View full abstract

To minimize the power consumption of an analog sigma-delta modulator (SDM), a fifth-order loop filter of the SDM has been realized with only three operational amplifiers (op-amp). The analog SDM with shared op-amp is applied to a class-D amplifier for a digital hearing aid. The class-D amplifier with the analog SDM has been realized in a standard 0.13-µm CMOS process. The maximum output power level of the class-D amplifier is 1.13-mW for a load with 46.5-Ω DC resistance. The total harmonic distortion+noise (THD+N) and the dynamic range (DR) of the class-D amplifier are 0.0038-% and 96-dB, respectively. The fifth-order analog SDM with shared op-amp consumes only 0.2-mW from a 1.2-V power supply.

View full abstract

A wide input range, compliant with electrochemical amperometric sensors interface circuit is proposed in this paper. The interface circuit consists of a potentiostat which is fabricated on PCB board and an interface ASIC which is realized in a single chip. The ASIC employs current integrator (CI) and transimpedance amplifier (TIA) to deal with the input current in the order of nA and µA separately, achieving the advantage of wide input range and high resolution. An incremental sigma-delta ADC is employed to digitize the transferring signal to achieve the feature of one-to-one mapping between input and output. The ASIC is fabricated in 0.18 µm 1P5M mixed-signal CMOS process, has a dynamic range of 120 dB, and consumes 4.2 mA.

View full abstract

A pasted FBG based cantilever beam accelerometer’s sensitization process method has been proposed in this paper. We have built the pasted FBG-based cantilever beam accelerometer’s sensitization process model. The sensor’s sensitivity was improved by adjusting glue thickness between FBG and cantilever beam. Theoretical model has been proved by ANSYS simulation and experimental analysis: Simulation analysis shows that when distance between fiber core and cantilever beam is greater than 0.4 mm, it can be used to enhance sensitivity. Experimental analysis shows that when distance between fiber core and cantilever beam is 1 mm, sensitivity of sensor is increased by 2.9 times compared with the conventional process, but it has no effect on the sensor dynamic characteristics. Compared with conventional sensitization method, it’s more general, and can be applied to all pasted FBG accelerometer for enhancing sensitivity.

View full abstract

This letter explores the performance of PCM-based swap storage and presents three management techniques. First, we attach PCM on DIMM slots to eliminate block I/O overhead and remove the context switching process while handling page faults. Second, we reduce the page size and turn off the read-ahead option to consider the high performance characteristics of PCM. Third, we decrease the DRAM memory size to save energy consumption without sacrificing the performance.

View full abstract

This paper presents the design of a broadband calculable dipole reference antenna with a 3 dB hybrid balun in the 1 GHz to 3 GHz frequency range. One dipole with a length resonant at 1.3 GHz was used to cover the 1 GHz to 3 GHz frequency range due to its suitable broadband characteristics. The design procedures are explained, and the design results show that the single broadband calculable dipole reference antenna with a hybrid balun can be characterized by power mismatch–loss component factors.

View full abstract

Frequency signature chipless RFID tag based on spurline resonator is presented in this letter. Resonant response of spurline is explained by analyzing the surface current distribution. Chipless tag consists of a data encoding circuit and two cross polarised monopole antennas. The tag has a data capacity of 16 bits in the range 2.13 to 4.1 GHz. Data capacity of data encoding circuit is enhanced by repositioning the spurlines. The prototype of the tag is fabricated on FR4 substrate. Developed tag can be used for cost effective identification of items in the industry.

View full abstract

This paper presents a delay-optimized floating point fused add-subtract (FAS) unit. A FAS unit is very useful for FFT and DCT butterfly operations since it can perform addition and subtraction of two floating point numbers simultaneously. The latency of critical path is reduced by using injection-based rounding method and performing parallel exponent adjustment. The proposed FAS is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that the proposed FAS requires roughly 60% area of two discrete adders. Comparison results show that our proposed FAS unit is 30% faster and 56% less area than the fastest FAS in previous work.

View full abstract