IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS
Xiaoge ZhuLei ZhouDanyu WuJin WuXinyu Liu
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2017 Volume 14 Issue 5 Pages 20170067

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Abstract

This paper presents an 8-channel time-interleaved SAR ADC. A novel sampling structure is proposed to improve the input bandwidth which also avoids time-skew calibration. The comparator offset cancellation is achieved by body voltage adjustment using low-power charge pump. Each channel has its own on-chip reference buffer to stable reference voltage and correct gain mismatches. The prototype is fabricated in 1P6M 0.13 µm CMOS technology. At 400 MS/s, the ADC achieves an SNDR of 50.84 dB and 45.7 dB at 19.1 MHz and 451 MHz, respectively. It consumes 200 mW, resulting in FOM of 1.76 pJ/con-step.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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