FBEL: Enhanced LLR optimization algorithm based on the VSER prediction by flag bits in the bit-flipping scheme

抄録

With the development of storage technology, NAND Flash’s reliability becomes more serious. The bit-flipping schemes and low-density parity-check (LDPC) codes are two effective methods to solve this problem. Motivated by error characteristics of NAND Flash and flag bits added by the bit-flipping scheme, an enhanced LLR optimization algorithm of LDPC is proposed based on the prediction of the threshold voltage state error rate (VSER) by flag bits. Compared with the conventional scheme, the proposed algorithm extends the data retention time to 25.44 times. The decoding iterations of LDPC are reduced by up to 87.74%.