A 0.7 V 4.2 μW 13 bit self-timed incremental NC-SMASH ADC with SAR-logic-based integrator

Abstract

This letter presents a self-timed incremental Noise-Cancelling Sturdy MASH (NC-SMASH) ADC for low-voltage event-driven applications. Employing the self-timed NC-SMASH architecture, it eliminates oversampled clocks and cancels the first-stage quantization error. A novel SAR-logic-based integrator is proposed to overcome design difficulties under low supply conditions. Its current-steering DAC (IDAC) combines a coarse-fine two-phase charging theme, utilizing correlated-level-shifting (CLS)-assisted self-cascoded fine current source, and achieves fully dynamic power consumption. Techniques that switch off noise-controlling capacitors of the first integrator comparator and data-weighted-averaging (DWA) units during later cycles of one-shot incremental conversion are used. This reduces power consumption without deteriorating performance. The proposed ADC is fabricated in 55 nm CMOS technology, occupying an active area of 0.69 mm². It achieves a measured 83.6 dB signal-to-noise ratio (SNR) with a conversion time of 2.06 ms, while consuming only 4.2 μW from 0.7 V supply. It corresponds to a Schreier Figure-of-Merit (FoM) of 161.2 dB, the best among all zero-crossing-based noise-shaping ADCs.