Designing special accelerators for mixed-precision and sparse convolutional neural networks (CNNs) is a very effective method to improve computational efficiency. However, few accelerators can support mixed bitwidth and sparsity at the same time, and most of them can only support layer-wise mixed bitwidth or element-wise sparsity, which make limited use of compressed CNNs. In order to fully utilize the benefits of model compression, it is of great significance to design accelerators that support fine-grained mixed bitwidth and bit-wise sparse computation. Therefore, this brief first proposes a hardware-efficient and precision-scalable sparse processing element (PE) that can support mixed bitwidth multiply-and-accumulate (MAC) operation and bit-wise sparse zero-skipping. Secondly, a fine-grained convolution acceleration method is proposed, which quantifies and encodes the valid bits of weight group to exploit the bit-wise sparsity of the high and low bits. Finally, the proposed fine-grained precision-scalable sparse accelerator is proposed and implemented on Xilinx ZC706 FPGA device, which achieves better accuracy and performance. When tested on VGG16, the proposed accelerator improves DSP efficiency by 1.77× to 3.84× compared to state-of-the-art accelerators.

In order to improve the signal quality in the RX (receiver), a 25 Gbps continuous-time linear equalizer (CTLE) based on 55 nm process design is proposed. The proposed circuit adds a pair of zero and pole that can modulate mid-frequency equalization, and it includes a new binaural structure negative capacitance circuit that can achieve a wider bandwidth compared to the traditional CTLE. The simulation results show that, when the 25 Gb/s NRZ signal is transmitted through the 35 cm FR4 PCB trace, the proposed circuit can compensate for a channel loss of 13 dB at the Nyquist frequency, the eye diagram opens up significantly with 0.95 UI eye width and 1.1 V voltage swing.

There are a large number of 2.45G weak energy signals in the environment, which can be collected and realized for applications by microwave wireless energy transfer systems (WMPT). However, the rectification efficiency of WMPT with Si MOSFET as the core rectifier component is low at 2.45G weak energy density. In this paper, a high carrier mobility composite strain GeOI material is proposed and designed, and the optimal crystal orientation/crystal plane of the composite strain GeOI PMOSFET channel is optimized and determined by quantum mechanics related theory. The GeOI PMOSFET device is simulated and designed using Silvaco software, while a half-wave rectifier circuit with a load of 0.5 pf and 30 kΩ is built in the Mixed-mode module, and its peak rectification efficiency can reach 42.1% at 3.89 dBm. The rectification efficiency at -12.1 dBm 2.45G weak energy density reaches 6.5%, which is 3.96 times higher than that of the equivalent body Si MOSFET.

This letter presents a self-timed incremental Noise-Cancelling Sturdy MASH (NC-SMASH) ADC for low-voltage event-driven applications. Employing the self-timed NC-SMASH architecture, it eliminates oversampled clocks and cancels the first-stage quantization error. A novel SAR-logic-based integrator is proposed to overcome design difficulties under low supply conditions. Its current-steering DAC (IDAC) combines a coarse-fine two-phase charging theme, utilizing correlated-level-shifting (CLS)-assisted self-cascoded fine current source, and achieves fully dynamic power consumption. Techniques that switch off noise-controlling capacitors of the first integrator comparator and data-weighted-averaging (DWA) units during later cycles of one-shot incremental conversion are used. This reduces power consumption without deteriorating performance. The proposed ADC is fabricated in 55 nm CMOS technology, occupying an active area of 0.69 mm². It achieves a measured 83.6 dB signal-to-noise ratio (SNR) with a conversion time of 2.06 ms, while consuming only 4.2 μW from 0.7 V supply. It corresponds to a Schreier Figure-of-Merit (FoM) of 161.2 dB, the best among all zero-crossing-based noise-shaping ADCs.

A low-area and low-temperature-coefficient (TC) bandgap reference (BGR) circuit using curvature compensation technology is presented. Comparing with traditional BGR with multiple BJT, four MOSFETs biased in their weak-inversion regions can produce a proportional-to-absolute-temperature (PTAT) voltage without consuming a great active area. In addition, a curvature compensation circuit was adopted to reduce the drift of temperature. The proposed BGR circuit has been implemented using a 0.18 um technology, occupying an area of 0.01 mm². Simulation results demonstrate that the BGR achieves average TC of 7.86 ppm/°C from -40°C to 125°C at 3.3 V and the line regulation (LR) of 0.048%/V between 2.7 and 3.6V supply voltage, respectively.

This letter proposes a peak coupling injection (PCI) technique to achieve low-phase-noise in a quadrature voltage-controlled oscillator (QVCO). By precisely injecting the coupling current at the peak of the oscillation waveform, the impulse sensitivity function (ISF) is minimized at the moment of current injection, thus significantly improving the phase noise of QVCO. The proposed PCI-QVCO is designed and verified using 0.13 μm SiGe BiCMOS technology. Measurement results indicated that our PCI-QVCO has a phase noise of -91 dBc/Hz at 1-MHz offset from 13 GHz, with a power consumption of 38 mW and a figure of merit (FOM) of -157 dBc/Hz. The die area is 0.70×0.87 mm².

We present an ultra-low power ternary SRAM (T-SRAM) with a storage capacity of 1.5 bit/cell, using a commercial 110-nm CMOS foundry for always-on applications, along with an analysis of its stability. By designing T-CMOS with SPICE compact model parameters, which are body-effect coefficient (m), peak electric field coefficient (C_EP), and gate width (W), band-to band tunneling current (I_BTBT) can be reduced to hundreds of fA range and it allows V_DD to scale down to 0.55 V. Finally, we experimentally demonstrate T-SRAM cell which static and dynamic powers are decreased to 4.5 × 10^-2 and 1.3 × 10^-7, respectively.

A novel digital-to-analog converter (DAC) switching scheme has been developed to improve the power efficiency of successive approximation register (SAR) analog-to-digital converters (ADCs). This scheme involves sampling the input signals on the bottom-plates of the most significant bit (MSB) capacitors, effectively eliminating the reset energy. The reference voltage V_REF is only switched during the third-bit cycle, avoiding more power consumption. Moreover, a one-sided two-level switching technique is utilized from the fourth-bit cycle onwards. As a result of this innovative switching approach, there is a 66.97% reduction in switching energy compared to the method proposed by Sanyal. The post-layout simulation results demonstrated that the proposed SAR ADC achieves the ENOB of 9.68 bits at a sampling rate of 20 KS/s, and consumes 36.9 nW of power in a 0.18-μm 1P6M CMOS process with a 0.6 V power supply, resulting in a figure of merit (FOM) of 2.25 fJ/conversion-step.

To reduce the switching loss of SiC MOSFET. In this paper, based on the reverse conduction process of SiC MOSFET in the third quadrant, the current flow direction and loss changes in the switching process are analyzed in detail, and it is found that the loss of the reverse conduction process is minimum at a specific dead time or load resistance. On this basis, an analytical model for the loss of SiC MOSFET reverse conduction process under different working conditions is established, and based on this model, a low loss strategy is proposed, that is, the output capacitor can discharge within the dead time by selecting the appropriate dead time and load resistance, so as to avoid discharging the output capacitor through the channel, so as to reduce the switching loss. The expressions for calculating dead time and load resistance are also given. Finally, the correctness of the low loss strategy is proved by the experimental results.

This paper presents a smart monolithic integrated IGBT gate driver integrated circuit (IC) which is suitable for the control of 3-phase inverter and power factor correction (PFC). The chip integrates seven channels on a single chip, comprising three high-side and three low-side channels for the control of 3-phase inverter section, and one low-side PFC channel for the control of PFC section. By providing the undervoltage protection (UV), overcurrent protection (OC), and fault logic control, abnormal functionality caused by accidents is suppressed to prevent the power inverter system from failing or malfunctioning. The chip is designed and fabricated using a 600 V 1.0 µm high voltage Bipolar-CMOS-DMOS (BCD) process, in order to achieve high and low voltage circuits monolithic integration, and occupies a core area of only 3500 µm × 2400 µm. Experimental results validated the functionality of the chip. Compared to conventional solutions, this chip has more functions and higher integration, which deliver a complete power stage solution for high performance and cost-effective applications.