抄録
A novel area-efficient on-chip feedback delay element (FDE) has been designed and evaluated in 0.18-µm CMOS technology. The circuit utilizes positive feedback to achieve both digitally controlled propagation delay and programmable duty cycle with only 9.5% silicon area of the conventional capacitor-loaded delay element (DE). The proposed FDE with monotonic delay step is suitable for use in area-sensitive and high-speed CMOS VLSI applications for memories and CPUs.
