抄録
Many DSP applications such as digital filters and linear transforms are composed of multiple constant multiplication (MCM) circuits. In hardware design of MCM circuits, it is important to decrease the hardware cost to the minimum. For a design of MCM circuits with minimum cost, it is a feasible approach to apply combinatorial optimization algorithms. However, if implemented as software, the time needed for optimization increases rapidly as the circuit scale increases. In the design procedures, circuit synthesis is the most time-consuming module, and it is called the most frequently. The purpose of this study is to develop a hardware-oriented circuit synthesis module using FPGAs to shorten the time spent on the design of MCM circuits.
