IEICE Electronics Express
Online ISSN : 1349-2543
Hardware implementation of a tessellation accelerator for the OpenVG standard
Seung Hun KimYunho OhKaram ParkWon Woo Ro
ジャーナル フリー

2010 年 7 巻 6 号 p. 440-446


The OpenVG standard has been introduced as an efficient vector graphics API for embedded systems. There have been several OpenVG implementations that are based on the software rendering of image. However, the software rendering needs more execution time and power consumption than hardware accelerated rendering. For the efficient hardware implementation, we merge eight pipeline stages in the original specification to four pipeline stages. The first hardware acceleration stage is the tessellation part which is one of the pipeline stages that calculates the edge of vector graphics. In this paper, we provide an efficient hardware design for the tessellation stage and claim this would eventually reduce the execution time and hardware complexity.

© 2010 by The Institute of Electronics, Information and Communication Engineers
前の記事 次の記事