抄録
This letter presents a DLL (Delay Locked Loop)-based CDR (Clock Data Recovery) design with a modified input data format. The proposed CDR recovers the clock and tracks the phase by the proposed training and real data patterns. The proposed input data formatting is done by inserting the ‘01’ pattern in every N-bit data. To prove the feasibility, a 2.4Gbps CDR is designed and simulated. The training and the real data pattern were formatted as the 10B12B for a high-performance display interface. The CDR achieves less jitter due to the DLL structure. The proposed CDR with the 10B12B format consumes approximately 8mA under 3.3V power supply using 0.25µm CMOS process.
