論文ID: 21.20240189
Approximate computing stands as a highly promising approach in curbing power consumption and enhancing energy efficiency in error-tolerant applications, such as image processing and neural networks. This brief introduces two unsigned approximate multiplier designs: MUL1, tailored for high-precision applications, and MUL2, optimized for low-power usage. Furthermore, we propose Approximate N-4 compressors, which are devised based on input reordering circuits, along with a novel approximate 4-2 compressor that align positive and negative approximations for input patterns sharing the same probability. These proposed approximate multipliers have been synthesized using 40nm technology, demonstrating remarkable improvements. In comparison to the exact multiplier, the first proposed multiplier boasts an 84.98% enhancement in the power-delay-area product (PDAP), while the second multiplier achieves an even more significant improvement of 97.22% in this parameter.
