抄録
To realize low-power wireless transceivers, it is necessary to improve the performance of frequency synthesizers, which are typically frequency multipliers composed of a phase-locked loop (PLL). However, PLLs generally consume a large amount of power and occupy a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFM), where a spurious signal is suppressed using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18µm 1P5M CMOS process. The core size is 10.8µm × 10.5µm. The power consumption of the ILO is 9.6µW at 250MHz, 255µW at 2.4GHz and 1.47mW at 4.8GHz. The phase noise is -105dBc/Hz at a 1MHz offset.
