Objective: Avoiding injection incompatibilities is important. At our hospital, pharmacists are present at the intensive care unit (ICU),where they manage drip lines and use a

table for injection incompatibilities. We assessed the risk of injection incompatibilities in the ICU and the contribution of pharmacists toward their avoidance.

Methods: We investigated the number of injections and main drip lines used for outpatients admitted to the general ward and ICU from an emergency setting. We further investigated inappropriate drip line conditions, subsequent interventions by pharmacists, and the actual number of injection incompatibilities. The investigation period lasted 1 year from April 2016 onward.

Results: The number of injections and drip lines used in the ICU was significantly higher than that used in the general ward (p<0.001). Patients in the ICU received multiple continuous intravenous injections from one drip line despite the number of main drip lines being high. Even using the

table, 78.3% inquiries made by nurses were related to injection incompatibilities. Fourteen inappropriate drip lines selected by nurses were associated with a risk of injection incompatibility; these occurred during the absence of pharmacists and involved a combination of continuous intravenous injections to be administered from a side line. Subsequently,pharmacists intervened and avoided injection incompatibilities. There was no report of injection incompatibilities in the ICU.

Conclusion: At ICU, the risk of injection incompatibilities is high and it is necessary to focus on the combination of injections to be administered from main drip lines and side lines as well as incompatibilities of multiple continuous intravenous injections to be administered from side lines. A

table is insufficient to avoid injection incompatibilities. Therefore, pharmacists can contribute to avoiding injection incompatibilities by maintaining constant presence in the ICU, designing drip line layouts, and proposing line selections.

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We developed BML browser for broadcasting system based on home servers. Five new functions, playback, search, segment table , program information and status , are implemented to this browser.

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Murataのアルゴリズムにルックアップテーブルの考え方を導入することによ り、同種アミノ酸配列だけの対応を考慮するタンパク質配列比較アルゴリズム を考案した。このアルゴリズムは、Murataのアルゴリズムに比べて、演算が10 倍ほど高速に行え、ギャップペナルティーを18にした時にほぼ同じアライン メントを得ることができた。また、FASTAより2、3倍演算は遅いが、より精 度の高い類似度を与えることも明らかにした。

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オブジェクト指向言語のJIT(just-in-time)コンパイラやネイティブコンパイラにおいて，仮想メソッド呼出しを高速化する最適化が重視されている．本研究は，仮想メソッド呼出しの際に行われるメソッド検索のうち冗長なものを削除し，最初に行われた適切なメソッド検索結果を再利用することによって，仮想メソッド呼出しのコストを低減する手法を提案する．本手法は，メソッド呼出しをインライン展開にする際に要求される受信オブジェクトの型の一意性を必要とせず．同じメソッド呼出しに対する受信オブジェクトの型の一致性だけに基づいて，冗長なメソッド検索を除去することができる．また，静的に型が決められないオブジェクトに対して，実行パスによっては型が一意に決定できる場合に，メソッド検索部を移動させることによって，受信オブジェクトの型を一意に変換し，メソッドを直接呼出に変換する効果ももつ．本手法は，既存の最適化手法と補間的に使用することができ，目的コードサイズを小さく抑える必要がある組込みシステムに対しても有効である．

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This paper presents a snow algorithm for the Advanced Microwave Scanning Radiometer (AMSR)and the AMSR for the Earth Observation System (AMSR-E). We validate the algorithm using snow-depth data recorded at the Coordinated Enhanced Observing Period (CEOP) Reference Site in Yakutsk, Russia. A new radiative transfer model for layered snow is developed by combining the 4-stream fast model and the dense media radiative model (DMRM); this model is then introduced into the new algorithm. The algorithm considers the effects of land-surface hydrological conditions under the snow layer and snow-panicle grain size on brightness temperatures in the microwave region by using the multi-frequency channels of AMSR and AMSR-E. The algorithm was validated at seven snow-measurement points within the CEOP Reference Site in Yakutsk from October 2002 to March 2003, corresponding to the first half of the third Enhanced Observing Period (EOP3).
We calculated the root mean square error (RMSE) based on the error between observed and estimated values and calculated the residual standard deviation (RSD) for all verification periods. We also calculated the proportion and RMSE of overestimated and underestimated values. The average RMSE is low (4.0 cm) and the average RSD is 2.8, indicating only minor variation. In addition, 56% of values were overestimated, and the average RMSE of the overestimated values was 3.9 cm; the average RMSE for the 44% of values that were underestimated was 2.4 cm. Accordingly, the estimated snow depth is in relatively good agreement with in situ data.
For the analyses undertaken at each site, we used the proposed algorithm to assess the influence of forest cover, frozen soil, and cloud cover on the process of estimating snow depth. We propose that such analyses are necessary when estimating snow depth.

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A Monte Carlo code simulating electron-photon showers was developed using the conventional technique which separates the electron slowing down into the continuous process and the discrete one. All the interactions in the discrete process, those are inelastic scattering, bremsstrahlung generation and positron annihilation in-flight, were taken into account. The table storage and method was adopted for randomly sampling the discrete processes. The tables were pre-digested by compiling the numerical data obtained from the deterministic calculations. The outline of sampling scheme and the details of calculational procedure are described. Some examples of the data preparation for sampling the electron energy at which a reaction occurs and the energy of emitted particles are shown for water. The present procedure is simple and useful when the development of the Monte Carlo code of electron-photon transport is undertaken.

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In this paper, a novel fast Gaussian blurring method that uses Look-Up Table (LUT) is presented for creating a real time Difference of Gaussian (DoG) pyramid. The LUT for fast and accurate Gaussian blur is obtained from the values calculated from one-dimensional (1D) Gaussian elements and pixel values of image. To evaluate the method, computation time and similarity with a conventional two-dimensional (2D) Gaussian blur are measured, and compared to other blurring methods. Based on the computational results, the proposed method shows good performance than other blurring methods such as box filter, Stack-blur, Romain Guy's method, and recursive Gaussian blur. The proposed method could be effectively applied to create the DoG pyramid for feature extraction.

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Memory-efficient Internet Protocol (IP)

with high speed is essential to achieve link-speed packet forwarding in IP routers. The rapid growth of Internet traffic and the development of optical link technologies have made IP a major performance bottleneck in core routers. In this paper, we propose a new IP route architecture based on hardware called Prefix-Route Trie (PR-Trie), which supports both IPv4 and IPv6 addresses. In PR-Trie, we develop a novel structure called Overlapping Hybrid Trie (OHT) to perform fast longest-prefix-matching (LPM) based on Multibit-Trie (MT), and a hash-based level matching query used to achieve only one off-chip memory access per . In addition, the proposed PR-Trie also supports fast incremental updates. Since the memory complexity in MT-based IP schemes depends on the level-partitioning solution and the data structure used, we develop an optimization algorithm called Bitmap-based Prefix Partitioning Optimization (BP²O). The proposed BP²O is based on a heuristic search using Ant Colony Optimization (ACO) algorithms to optimize memory efficiency. Experimental results using real-life routing tables prove that our proposal has superior memory efficiency. Theoretical performance analyses show that PR-Trie outperforms the classical Trie-based IP algorithms.

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Network coordinates (NCs) enable the efficient and accurate estimation of network latency by mapping the geographical relationship among all nodes to Euclidean space. Many researchers have proposed NC-based strategies to reduce the latency of distributed hash tables (DHTs). However, these strategies are limited in the improvement of the latency; the nearest node to which a query should be forwarded is not always included in the consideration scope of a node. This is because conventional latency improvement strategies assign node IDs independent of the underlying physical network and still have the possibility of detour routing. In this paper, we propose an NC-based method of constructing a topology-aware DHT by Proximity Identifier Selection (PIS/NC). PIS/NC constructs a logical ID space of a DHT from the Euclidean space constructed by NCs; a node ID corresponds to the network coordinate of the node. By doing this, the consideration scope of a node always contains the nearest node, thus, we can expect a great reduction in latency. Unlike the conventional PIS strategy that poses unavoidable issues due to uneven ID distribution, PIS/NC tries to moderate these issues by a simple optimization, provided by a PIS/NC stabilizer. The PIS/NC stabilizer detects an uneven distribution of node IDs locally, and then recalculates some IDs so that the unevenness is moderated. As case studies, this paper presents Canary and Harpsichord, which are PIS/NC-based CAN and Chord, respectively. Simulation results show that PIS/NC-based DHTs improve latency. Under the environment using the Transit-Stub model, where SAT-Match and DHash++ are only able to reduce the median latency by 19% of CAN and 9% of Chord, respectively, Canary and Harpsichord reduce it by 40% and 35%, respectively. We also verify that the PIS/NC stabilizer moderates the non-uniform distribution of node IDs.

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Network coordinates (NCs) enable the efficient and accurate estimation of network latency by mapping the geographical relationship among all nodes to Euclidean space. Many researchers have proposed NC-based strategies to reduce the latency of distributed hash tables (DHTs). However, these strategies are limited in the improvement of the latency; the nearest node to which a query should be forwarded is not always included in the consideration scope of a node. This is because conventional latency improvement strategies assign node IDs independent of the underlying physical network and still have the possibility of detour routing. In this paper, we propose an NC-based method of constructing a topology-aware DHT by Proximity Identifier Selection (PIS/NC). PIS/NC constructs a logical ID space of a DHT from the Euclidean space constructed by NCs; a node ID corresponds to the network coordinate of the node. By doing this, the consideration scope of a node always contains the nearest node, thus, we can expect a great reduction in latency. Unlike the conventional PIS strategy that poses unavoidable issues due to uneven ID distribution, PIS/NC tries to moderate these issues by a simple optimization, provided by a PIS/NC stabilizer. The PIS/NC stabilizer detects an uneven distribution of node IDs locally, and then recalculates some IDs so that the unevenness is moderated. As case studies, this paper presents Canary and Harpsichord, which are PIS/NC-based CAN and Chord, respectively. Simulation results show that PIS/NC-based DHTs improve latency. Under the environment using the Transit-Stub model, where SAT-Match and DHash++ are only able to reduce the median latency by 19% of CAN and 9% of Chord, respectively, Canary and Harpsichord reduce it by 40% and 35%, respectively. We also verify that the PIS/NC stabilizer moderates the non-uniform distribution of node IDs.

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This paper presents a method to compile the Standard ML module language into a flattened intermediate language. An innovative point on this approach lies in viewing a functor as a code template with place holders representing the functor arguments. Each functor application fills these place holders in the code template with the actual functor argument and generates a fresh structure. After this compilation, module language constructs are all eliminated. This method allows us to compile the full set of Standard ML language into a typed intermediate language that contains no special mechanism for module, and provides a simpler model for separate compilation. The proposed compilation method has been successfully implemented in the SML# compiler, which demonstrates the feasibility of the method. This paper also reports the details of our implementation.

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In the era of IPv6, since the number of IPv6 addresses rapidly increases and the required speed is more than Giga lookups per second (GLPS), an area-efficient and high-speed IP architecture is desired. This paper shows a parallel index generation unit (IGU) for memory-based IPv6 architecture. To reduce the size of memory in the IGU, we use a linear transformation and a row-shift decomposition. A single-memory realization requires O(2^l log k) memory size, where l denotes the length of prefix, while the realization using IGU requires O(kl) memory size, where k denotes the number of prefixes. In IPv6 prefix , since l is at most 64 and k is about 340 K, the IGU drastically reduces the memory size. Also, to reduce the cost, we realize the parallel IGU by using both on-chip and off-chip memories. We show a design algorithm for the parallel IGU to store given off-chip and on-chip memories. The parallel IGU has a simple architecture and performs by using complete pipelines those insert the pipeline registers in all the paths. We loaded more than 340 K IPv6 pseudo prefixes on the Xilinx Virtex 6 FPGA with off-chip DDRII+ Static RAMs (SRAMs). Its speed is 1.100 giga lookups per second (GLPS) which is sufficient for the required speed for a next generation 400 Gbps link throughput. As for the normalized area and speed, our implementation outperforms existing FPGA implementations.

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High-speed IP address with fast prefix update is essential for designing wire-speed packet forwarding routers. The developments of optical fiber and 100Gbps interface technologies have placed IP address as the major bottleneck of high performance networks. In this paper, we propose a novel structure named Compressed Multi-way Prefix Tree (CMPT) based on B+ tree to perform dynamic and scalable high-speed IP address . Our contributions are to design a practical structure for high-speed IP address suitable for both IPv4 and IPv6 addresses, and to develop efficient algorithms for dynamic prefix insertion and deletion. By investigating the relationships among routing prefixes, we arrange independent prefixes as the search indexes on internal nodes of CMPT, and by leveraging a nested prefix compression technique, we encode all the routing prefixes on the leaf nodes. For any IP address, the longest prefix matching can be made at leaf nodes without backtracking. For a forwarding table with u independent prefixes, CMPT requires O(log _mu) search time and O(mlog _mu) dynamic insert and delete time. Performance evaluations using real life IPv4 forwarding tables show promising gains in and dynamic update speeds compared with the existing B-tree structures.

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Self-localization of the mobile robot using RFID system generally requires a table which relates the ID of each tag with its position. However, it is tedious for a human worker to manually build the table. This paper proposes a method to automatically build the table by a simple mobile robot without global position measurement function. Given the small number of RFID tags with their accurate position data, the method successfully build the table for many other RFID tags whose position is unknown in advance.

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Although IP address schemes using ternary content addressable memory (TCAM) can perform high speed packet forwarding, TCAM is much more expensive than ordinary memory in implementation cost. As a low-cost solution, binary search algorithms such as a binary trie or a binary search tree have been widely studied. This paper proposes an efficient IP address scheme using balanced binary search with minimal entries and optimal prefix vectors. In the previous scheme with prefix vectors, there were numerous pairs of nearly identical entries with duplicated prefix vectors. In our scheme, these overlapping entries are combined, thereby minimizing entries and eliminating the unnecessary prefix vectors. As a result, the small balanced binary search tree can be constructed and used for a software-based address in small-sized routers. The performance evaluation results show that the proposed scheme offers faster speeds along with reduced memory requirements.

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