抄録
This paper proposes a new scan-based BIST scheme that implements weighted random pattern testing by loading different scan input data into scan chains with proper probabilities. These scan input data include previous scan values into the scan chains, pseudorandom data generated by test pattern generator, test responses collected by the scan chains, and the complement of test responses. Due to increasing the correlation among adjacent test stimulus bits, the proposed method decreases the switching activity during scan shift. Meanwhile our method applies the four kinds of test data with different probabilities to maximize test effectiveness. A greedy procedure is proposed to select the proper probabilities that the four kinds of data are selected for each scan chain. When comparing with an existing method called LT-RTPG, experimental results for larger benchmark circuits of ISCSAS89 show that the proposed method can significantly reduce shift test power while providing higher fault coverage.
