Journal of The Japan Institute of Electronics Packaging
Online ISSN : 1884-121X
Print ISSN : 1343-9677
ISSN-L : 1343-9677
2015 JIEP Award-Technical Development
Development of Ultra Low CTE (Coefficient of Thermal Expansion) Substrate Materials for Semiconductor Package
Shin TakanezawaHikari MuraiMasato MiyatakeTomohiko KotakeShintaro HashimotoShinichiro AbeMasaaki TakekoshiMasahisa OseKoji MoritaTomio Iwasaki
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2016 Volume 19 Issue 6 Pages 421-426

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Abstract
Semiconductor packaging technology is moving towards three-dimensional packages due to the need for high speed/high performance in mobile devices. Consequently, laminate materials for the packages of today need to be thinner and thinner. However, the lower stiffness of the total substrate leads to increased warpage of packages made with the thinner materials. Therefore, in order to reduce this warpage, it is necessary to reduce the coefficient of thermal expansion (CTE) of the laminate materials. At Hitachi Chemical, we have developed laminate materials by focusing attention on polycyclic aromatic resins, and we have investigated indicators for low CTE resins using molecular simulation technology. This paper introduces (1) the features of those polycyclic aromatic resins that show low CTE and their stacking effects, and (2) the design of low CTE resins with the help of compatibilizing energy as an indicator.
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© 2016 The Japan Institute of Electronics Packaging
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